direkt zum Inhalt springen

direkt zum Hauptnavigationsmenü

Sie sind hier

TU Berlin

Inhalt des Dokuments

Speeding up Vision Algorithms for Real-Time Applications Using Reconfigurable Architectures: A Comprehensive Study

Abstract

The demand for real-time vision systems is increasing recently with the advance of computer architectures and artificial intelligent systems. Robots, unmanned planes, and driver assistant systems are examples of such systems. Reconfigurable architectures such as FPGA are recently attracting attention as rapid high speed implementation platform for real time systems due to their parallel nature. In this research proposal existed algorithms will be investigated in order to find potential parts of the algorithm that can benefit from reconfigurable architectures such as FPGA. This will help building a library of hardware cores that can be used to build a wide range of real-time applications.

Introduction

Several attempts have been made to move real-time vision algorithms into reconfigurable architectures such as [1][2][3][4]. In all these trials a specific algorithm was selected and analyzed for its implementation, for example, on FPGA. The focus of these studies was on that specific application, which results in a significant result for the application under study.

A comprehensive study of vision algorithms independent from the application being implemented will give more insight of these algorithms and allows building a library of components that can be used to build a wider range of algorithms and applications.

Methodology

Lupe

In this research project we aim to investigate the possible enhancments and implementations for vision algorithms on FPGA. This involves the following steps:

  1. Investigate Image Processing and Computer Vision Algorithms

    1. Memory Usage
    2. Parallel Processing.

  2. Build a library of hardware components that can be used to build complex algorithms

    1. Depends on algorithm analysis
    2. Based on several applications

  3. Components

    1. Pixel based blocks
    2. Integrated Image Processing Units with Code blocks
    3. Components can be arranged in various parallel processing stages

  4. This will compose a framework with a massively parallel computation nature. The figure presents the proposed system.
  5. Applications

    1. Licence Plate Recognition (LPR).
    2. Lane Detection, and Sign Detection for Automobile Industry
    3. Robots and Robot vision

Expected Results

A framework for implementing vision algorithms on reconfigurable architectures, will be the main deliverable of this research project. This framework will be verified using various applications that can be found in the industry.

Objectives

Students (Master/Bachelor) will be involved in several tasks of this project. The main objectives are:

  1. Build the hardware framework, including its component
  2. Implement a specific application using the framework
  3. Custom implementations that are tailored towards a specific application  

A concrete assignment in the scope of this project will be defined based on the skills and preferences of an interested candidates.

Prerequisites

The following skills are important for the work in this project. Knowledge of some or all of them will be an advantage:

  1. Digital hardware design
  2. VHDL/FPGA design flow
  3. Image Processing and Signal Processing

Contact Persons

Zusatzinformationen / Extras

Quick Access:

Schnellnavigation zur Seite über Nummerneingabe

Auxiliary Functions