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Inhalt des Dokuments

Multicore Architectures

Informations
Course
Multicore Architectures
Course Number
0433 L 333
Modul Duration
one semester
Credits Points
(according to ECTS)
4 SWS / 6 ETCS
Catalog
1 and 6
Code Designation
MINF‐SE‐MAR
module description
Period
Lecture: 15.10.2012 - 11.02.2013
Lab: 29.10.2012 - 14.01.2013
Date
Lecture: Monday, 10-12
Lab: Monday, 14-16
Room
Lecture: TA201
Lab: EN 732
Contact
mca@aes.tu-berlin.de

Content

  • Cache coherence protocols and memory consistency models
  • Synchronization and Transactional memory
  • Streaming processors, systolic arrays, and dataflow processors
  • Vector processors
  • Graphics Processing Units (GPUs)
  • Thread speculation
  • Interconnection networks, routing, collective communication operations
  • Amdahl’s law in the multicore era, scalability analysis
  • Latency hiding techniques, double buffering
  • Homogeneous vs. heterogeneous multi-cores, Multiprocessor Systems on Chip (MPSoCs)
  • Power consumption, voltage/frequency scaling
  • Reliability, fault tolerance
  • Virtualization
  • 3D integration
  • Real-time issues, dataflow programming models

ISIS

Slides and further information can be found on ISIS.

The password for the ISIS page is given in the lecture, lab or can be asked via a Tu-Berlin Emailadress.

Tutorial

The tutorial is a mixture of assignments and lab hours.

The assignments should consolidate the topic from the lecture. Some graded homeworks must be done.

During the lab the students must parallelize some serial programs using the pthread libraries and a novel component-oriented programming model C2. Basic knowledge of C and C++ is required. The lab assignments will be graded.

Module Examination and Grading Procedures

The exam consists of several achievements (Prüfungsäquivalente Studienleistungen): The practical work contributes with 50% and the final test with 50%. Both parts must be passed to complete the entire module.

Zusatzinformationen / Extras

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