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Welcome at AES

Lupe

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

News

24.05.2018: AES at RAW@IPDPS 2018.

Lupe

Matthias Göbel attended the 25th Reconfigurable Architectures Workshop (RAW) at the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018). He presented the paper “An Application-Specific Memory Management Unit for FPGA-SoCs” by Matthias Göbel, Ilja Behnke, Ahmed Elhossini and Ben Juurlink. During the workshop, it was announced that the paper had been one out of three candidates for the Best Short Paper Award.

The 25th Reconfigurable Architectures Workshop (RAW 2018) has been held in Vancouver, British Columbia, Canada in May 2018. RAW 2018 is associated with the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing.

More information can be found at http://www.ipdps.org/ipdps2018/.

15.05.2018: Biao Wang successfully completed his PhD defense.

Lupe

M.Sc. Biao Wang successfully completed his PhD defense on Tuesday 15th May 2018. His thesis title was: "High-performance Video Decoding using Graphics Processing Units”.
Congratulation Dr. Wang for your success and we wish you the best in your future! 

18.04.18: Sohan Lal Selected With Student Grant to Attend ACACES 2018.

Lupe

Sohan Lal has been selected with student grant to attend the "Fourteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2018). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.
ACACES 2018 will take place in Fiuggi, Italy, from July 8th to July 14th, 2018.
For more information please visit: http://acaces.hipeac.net/2018/index.php

More news can be found here.

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Auxiliary Functions

Chair:
Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Request appointment

Secretary's office:
Sara Tennstedt
Room E-N 645
Tel. +49.30.314-73130
Consultation hours:
Mo, Tue, Wed and Thu 10:00 am - 12:00 am
or with appointment


Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17- 6. OG
D-10587 Berlin
Germany

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