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Welcome at AES

Lupe

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

News

26.04.2017: PC memberships Ben Juurlink.

Lupe

Prof. Ben Juurlink, head of the AES research group, currently is a member of several program committees:

  • SBAC-PAD (Int. Conf. on Computer Architecture and High Performance Computing),
  • SCOPES (Int. Workshop on Software and Compilers for Embedded Systems),
  • SAMOS (Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation), and
  • PARS (Workshop of the special interest group on parallel algorithms, parallel computer structures and parallel system software within the German Informatics Societies (GI/ITG)).

24.04.2017: Prof. Castrillon of TU Dresden guest lecturer for an AES course.

Lupe

We are very pleased to welcome Prof. Jeronimo Castrillon as a guest lecturer for the embedded systems architecture course during this summer. His compiler expertise will add a valuable contribution to the group's curricular activities.

More information about the Chair for Compiler Construction at TU Dresden can be found on the corresponding website: https://cfaed.tu-dresden.de/ccc-about

07.04.2017: Matthias Göbel, Ahmed Elhossini and Ben Juurlink receive Best Paper Award at ARC 2017 .

Lupe

Matthias Göbel, Ahmed Elhossini and Ben Juurlink received the Best Paper Award at the 13th International Symposium on Applied Reconfigurable Computing (ARC 2017) in Delft, NL for their paper "A Quantitative Analysis of the Memory Architecture of FPGA-SoCs". The work is co-authored by Chi Ching Chi and Mauricio Alvarez-Mesa of Spin Digital, a spin-off of AES.

In this paper, we analyze the various memory and communication interconnects found in FPGA-SoCs, particularly the Zynq-7020 and Zynq-7045 from Xilinx and the Cyclone V SE SoC from Intel. Issues such as different access patterns, cache coherence and full-duplex communication are analyzed, for both generic accesses as well as for a real workload from the field of video coding. Furthermore, the paper shows that by carefully choosing the memory interconnect networks as well as the software interface, high-speed memory access can be achieved for various scenarios.

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Auxiliary Functions

Chair:
Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Fax +49.30.314-22943
Asking for an appointment

Secretary's office:
Imke Weitkamp
Jana Pilz
Sara Tennstedt (parental leave)
Room E-N 645
Tel. +49.30.314-73130
Fax +49.30.314-22943
Consultation hours:
Thur 9:00 am - 12:00 am
Phone hours:
Thur 9:00 am - 4:00 pm
or with appointment


Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin
Germany

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