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Welcome at AES

Lupe

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

02.02.2017: AES at Intel AI Technical workshop in Munich.

Dr. Ahmed Elhossini is attending Intel AI Technical workshop, which is held at the same time as OOP 2017, Munich. This is a full day technical workshop for software developers and data scientists. The workshop will be conducted by technical experts from Intel covering following topics: • Intel Software development tools and libraries for Machine Learning and Deep Learning • Optimized Deep Learning frameworks for Intel Architecture • Tools and frameworks from Nervana Systems For more information please check the following link: http://ai-day2017.com/munich/technical-workshop.html more to: 02.02.2017: AES at Intel AI Technical workshop in Munich.

Research Seminar

  • 23.02.2017-10:00: "Syntax Element Partitioning for high-throughput HEVC CABAC Decoding". Philipp Habermann.
more to: Research Seminar

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Auxiliary Functions

Chair:
Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Fax +49.30.314-22943
Asking for an appointment

Secretary's office:
Imke Weitkamp
Jana Pilz
Sara Tennstedt (parental leave)
Room E-N 645
Tel. +49.30.314-73130
Fax +49.30.314-22943
Consultation hours:
Mo and Thur 9:00 am - 12:00
Tue 15:00 - 18:00
and with registration


Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin
Germany

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