Page Content
| Name | Thema | Datum |
|---|---|---|
| Biao Wang | High-performance Video Decoding using
Graphics Processing
Units |
05/2018 |
| Tamer Dallou | Enhancing the Scalability of Many-core Systems – Towards
Utilizing Fine-Grain Parallelism in Task-Based Programming
Models | 12/2017 |
| Kristian
Manthey | A Reconfigurable
Architecture for Real-Time Image Compression On-Board
Satellites | 10/2017 |
| Name | Thema | Datum |
|---|---|---|
| Daniel Schürmann | OpenMP Accelerator Offloading with OpenCL using
SPIR-V | 05/2018 |
| Nicolas Morini | A Study of Vectorization on ARM | 04/2018 |
| Jonas Tröger | An Evaluation of a
High-level Synthesis Tool for FPGAs | 11/2017 |
| Susheel Prakash Puranik | Limits
of Instruction-Level Parallelism (ILP) 2017 | 11/2017 |
| Andrès Gunnarson | Design and
Implementation of a low-power Neural Network algorithm for heartbeat
detection and classification from raw ECG | 11/2017 |
| Christina Quast | Development of a RICH Particle Identification
Algorithm on Intel’s Knight’s Landing Platform |
11/2017 |
| Siby Thachil | Minimizing
Interference between Multiple Time-of-Flight Cameras | 11/2017 |
| Wenbo Li | Quantitative Analysis of
Advanced Computer Architecture Technique: Dynamic Exploitation of
ILP | 10/2017 |
| Ahmad Chamas | Adaptive Face Recognition Using Convolutional Neural
Network | 09/2017 |
| Robert P. Hering | Embedded Load Balancing | 03/2017 |
| Ahmed Mohamed Zaky Osman | HEVC
acceleration on MPPA platform | 02/2017 |
| Felix Goroncy | Automated
Characterization of GPU Features Using OpenCL
Microbenchmarks | 02/2017 |
| Sanjay Santhosh Kumar | Investigation of real-time Ethernet based fieldbus
protocols for power electronic devices | 01/2017 |
| Xu Cao | Optimising HEVC Decoding
using Intel AVX512 SIMD Extensions | 01/2017 |
| Beatrice Tîrziu | Memory Subsystem
Performance Evaluation of the Kalray MPPA | 01/2017 |
| Name | Thema | Datum |
|---|---|---|
| Nils Schubert | Power Modelling for FPGA Design Space
Exploration | 10/2019 |
| Kai Norman Clasen | Evaluating the Memory Architecture of the Zynq
Ultrascale+ FPGA-SoC | 10/2018 |
| Hannes Kadlik | SIMD Erweiterungen
für die RISC-V ISA | 04/2018 |
| Lars Schymik | Design and
Implementation of a Configurable Convolution Filter for Deep
Learning | 10/2017 |
| Max Uffke Drechsler | A Generic Userspace Hardware Abstraction Layer for Linux
SoCs | 10/2017 |
rtations/submitted_theses_and_dissertations/archive/par
ameter/en/font2/maxhilfe/
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