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Embedded Systems ArchitectureProf. Dr. Ben Juurlink

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Prof. Dr. Ben Juurlink

Biography

Lupe

Prof. Dr. Ben Juurlink received the M.Sc. degree from Utrecht University, Utrecht, The Netherlands, and the Ph.D. degree from Leiden University, Leiden, The Netherlands, in 1992 and 1997, respectively.

In 1997-1998 he worked as a post-doctoral researcher at the Heinz Nixdorf Institute in Paderborn, Germany, and from 1998 to 2009 he was a faculty member (first assistant professor, then associate professor) of the Computer Engineering Laboratory of Delft University of Technology, Delft, The Netherlands. Currently, he is professor for Embedded Systems Architectures in the Faculty of Electrical Engineering and Computer Science of Berlin University of Technology, Berlin, Germany. He is also co-founder of Spin Digital GmbH.

Dr. Juurlink’s research interests include multi- and many-core processors, reconfigurable computing, and the art of mapping applications effectively and efficiently to computer architectures. He has (co-)authored more than 130 articles in international conferences and journals, and received best paper awards at the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS) in 2002, and at the third IEEE International Conference on Consumer Electronics – Berlin (ICCE-Berlin). He has also received a Technology Transfer Award from the HiPEAC Network of Excellence for transferring some of the video coding technology that has been developed in his group to a Greece-based SME.

Dr. Juurlink is a senior member of the ACM and a senior member of the IEEE. He has been the Principal Investigator of several national research projects, Work Package leader in several European projects, and Coordinator of the EU projects LPGPU, Film265, and LPGPU2. He has served on many program committees, is an editor of the Elsevier journal on Microprocessors and Microsystems: Embedded Hardware Design, and was the general co-chair of the HiPEAC conference in 2013.

Professional Experience

Professor for Embedded Systems Architectures


Berlin University of Technology, Germany


01/2010 -
present


Associate professor


Delft University of Technology, Netherlands


02/2007 - 12/2009


Director of education for master's programs in Computer Engineering and Embedded Systems


Delft University of Technology, Netherlands


09/2006 - 12/2009


Assistant professor


Delft University of Technology, Netherlands


09/1999 - 01/2007


Postdoctoral fellow


Delft University of Technology, Netherlands


09/1998 - 08/1999


Postdoctoral fellow


Paderborn University, Germany


01/1997 - 07/1998


Postdoctoral fellow


Leiden University, Netherlands


09/1996 - 12/1996


Visiting researcher


Max-Planck-Institut für Informatik, Saarbrücken, Germany


02/1995


Research assistant


Leiden University, Netherlands


09/1992 - 08/1996


Teaching assistant


Utrecht University, Netherlands


09/1990 - 01/1992


Education

PhD degree in computer science


Leiden University, Netherlands. Thesis title: Computational models for parallel computers


02/1997


MSc degree in computer science


Utrecht University, Netherlands


08/1992


Publications

Reconfigurable architecture for real-time image compression on-board satellites
Citation key doi:10.1117/1.JRS.9.097497
Author Kristian Manthey and David Krutz and Ben Juurlink
Pages 097497
Year 2015
ISBN 1931-3195
DOI 10.1117/1.JRS.9.097497
Journal Journal of Applied Remote Sensing
Volume 9
Number 1
Abstract Abstract. A high-speed image compression architecture with region-of-interest (ROI) support and with flexible access to compressed data based on the Consultative Committee for Space Data Systems 122.0-B-1 image data compression standard is presented. Modifications of the standard permit a change of compression parameters and the reorganization of the bit stream after compression. An additional index of the compressed data is created, which renders it possible to locate individual parts of the bit stream. On request, stored images can be reassembled according to the application’s needs and as requested by the ground station. Interactive transmission of the compressed data is possible such that overview images can be transmitted first followed by detailed information for the ROI. The architecture was implemented for a Xilinx Virtex-5QV and a single instance is able to compress images at a rate of 200  Mpx/s at a clock frequency of 100 MHz. The design ensures that all parts of the system have a high utilization and parallelism. A Virtex-5QV allows compression of images with a width of up to 4096 px without external memory. The power consumption of the architecture is ∼4  W. This example is one of the fastest implementations yet reported and sufficient for future high-resolution imaging systems.
Link to publication Download Bibtex entry

Older Publications

Further Publications of Prof. Juurlink  are here available.

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