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Prof. Dr. Ben Juurlink

Biography

Lupe

Prof. Dr. Ben Juurlink received the M.Sc. degree from Utrecht University, Utrecht, The Netherlands, and the Ph.D. degree from Leiden University, Leiden, The Netherlands, in 1992 and 1997, respectively.

In 1997-1998 he worked as a post-doctoral researcher at the Heinz Nixdorf Institute in Paderborn, Germany, and from 1998 to 2009 he was a faculty member (first assistant professor, then associate professor) of the Computer Engineering Laboratory of Delft University of Technology, Delft, The Netherlands. Currently, he is professor for Embedded Systems Architectures in the Faculty of Electrical Engineering and Computer Science of Berlin University of Technology, Berlin, Germany. He is also co-founder of Spin Digital GmbH.

Dr. Juurlink’s research interests include multi- and many-core processors, reconfigurable computing, and the art of mapping applications effectively and efficiently to computer architectures. He has (co-)authored more than 130 articles in international conferences and journals, and received best paper awards at the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS) in 2002, and at the third IEEE International Conference on Consumer Electronics – Berlin (ICCE-Berlin). He has also received a Technology Transfer Award from the HiPEAC Network of Excellence for transferring some of the video coding technology that has been developed in his group to a Greece-based SME.

Dr. Juurlink is a senior member of the ACM and a senior member of the IEEE. He has been the Principal Investigator of several national research projects, Work Package leader in several European projects, and Coordinator of the EU projects LPGPU, Film265, and LPGPU2. He has served on many program committees, is an editor of the Elsevier journal on Microprocessors and Microsystems: Embedded Hardware Design, and was the general co-chair of the HiPEAC conference in 2013.

Professional Experience

Professor for Embedded Systems Architectures


Berlin University of Technology, Germany


01/2010 -
present


Associate professor


Delft University of Technology, Netherlands


02/2007 - 12/2009


Director of education for master's programs in Computer Engineering and Embedded Systems


Delft University of Technology, Netherlands


09/2006 - 12/2009


Assistant professor


Delft University of Technology, Netherlands


09/1999 - 01/2007


Postdoctoral fellow


Delft University of Technology, Netherlands


09/1998 - 08/1999


Postdoctoral fellow


Paderborn University, Germany


01/1997 - 07/1998


Postdoctoral fellow


Leiden University, Netherlands


09/1996 - 12/1996


Visiting researcher


Max-Planck-Institut für Informatik, Saarbrücken, Germany


02/1995


Research assistant


Leiden University, Netherlands


09/1992 - 08/1996


Teaching assistant


Utrecht University, Netherlands


09/1990 - 01/1992


Education

PhD degree in computer science


Leiden University, Netherlands. Thesis title: Computational models for parallel computers


02/1997


MSc degree in computer science


Utrecht University, Netherlands


08/1992


Publications

A Predictor-Based Power-Saving Policy for DRAM Memories
Citation key Thomas2012:mempred
Author Gervin Thomas and Karthik Chandrasekar and Benny Akesson and Ben Juurlink and Kees Goossens
Title of Book Digital System Design (DSD), 2012 15th Euromicro Conference on
Pages 882 -889
Year 2012
DOI 10.1109/DSD.2012.11
Month sept.
Note Print ISBN: 978-1-4673-2498-4
Abstract Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings. In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%.
Link to publication Download Bibtex entry

Older Publications

Further Publications of Prof. Juurlink  are here available.

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