Inhalt des Dokuments
- © B.Juurlink
Prof. Dr. Ben Juurlink received the M.Sc. degree from Utrecht University, Utrecht, The Netherlands, and the Ph.D. degree from Leiden University, Leiden, The Netherlands, in 1992 and 1997, respectively.
In 1997-1998 he worked as a post-doctoral researcher at the Heinz Nixdorf Institute in Paderborn, Germany, and from 1998 to 2009 he was a faculty member (first assistant professor, then associate professor) of the Computer Engineering Laboratory of Delft University of Technology, Delft, The Netherlands. Currently, he is professor for Embedded Systems Architectures in the Faculty of Electrical Engineering and Computer Science of Berlin University of Technology, Berlin, Germany. He is also co-founder of Spin Digital GmbH.
Dr. Juurlink’s research interests include multi- and many-core processors, reconfigurable computing, and the art of mapping applications effectively and efficiently to computer architectures. He has (co-)authored more than 130 articles in international conferences and journals, and received best paper awards at the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS) in 2002, and at the third IEEE International Conference on Consumer Electronics – Berlin (ICCE-Berlin). He has also received a Technology Transfer Award from the HiPEAC Network of Excellence for transferring some of the video coding technology that has been developed in his group to a Greece-based SME.
Dr. Juurlink is a senior member of the ACM and a senior member of the IEEE. He has been the Principal Investigator of several national research projects, Work Package leader in several European projects, and Coordinator of the EU projects LPGPU, Film265, and LPGPU2. He has served on many program committees, is an editor of the Elsevier journal on Microprocessors and Microsystems: Embedded Hardware Design, and was the general co-chair of the HiPEAC conference in 2013.
Professor for Embedded Systems Architectures || Berlin University of Technology,
Germany || 01/2010 - |
|Associate professor ||Delft University of Technology,
Netherlands ||02/2007 -
of education for master's programs in Computer Engineering and
Embedded Systems ||Delft
University of Technology, Netherlands
||09/2006 - 12/2009|
|Assistant professor ||Delft University of Technology,
Netherlands ||09/1999 -
||Delft University of Technology, Netherlands ||09/1998 - 08/1999|
University, Germany ||01/1997
||Leiden University, Netherlands ||09/1996 - 12/1996|
||Max-Planck-Institut für Informatik, Saarbrücken,
|Research assistant ||Leiden University,
Netherlands ||09/1992 -
|Teaching assistant ||Utrecht University, Netherlands ||09/1990 - 01/1992|
| PhD degree in computer
science || Leiden
University, Netherlands. Thesis title: Computational models for
parallel computers ||
|MSc degree in computer science ||Utrecht University, Netherlands ||08/1992|
|Author||Biao Wang and Diego F. de Souza and Mauricio Alvarez-Mesa and Chi Ching Chi and Ben Juurlink and Aleksandar Ilic and Nuno Roma and Leonel Sousa|
|Journal||International Journal of Parallel Programming|
|Abstract||In the High Efficiency Video Coding (HEVC) standard, multiple decoding modules have been designed to take advantage of parallel processing. In particular, the HEVC in-loop filters (i.e., the deblocking filter and sample adaptive offset) were conceived to be exploited by parallel architectures. However, the type of the offered parallelism mostly suits the capabilities of multi-core CPUs, thus making a real challenge to efficiently exploit massively parallel architectures such as Graphic Processing Units (GPUs), mainly due to the existing data dependencies between the HEVC decoding procedures. In accordance, this paper presents a novel strategy to increase the amount of parallelism and the resulting performance of the HEVC in-loop filters on GPU devices. For this purpose, the proposed algorithm performs the HEVC filtering at frame-level and employs intrinsic GPU vector instructions. When compared to the state-of-the-art HEVC in-loop filter implementations, the proposed approach also reduces the amount of required memory transfers, thus further boosting the performance. Experimental results show that the proposed GPU in-loop filters deliver a significant improvement in decoding performance. For example, average frame rates of 76Â frames per second (FPS) and 125Â FPS for UltraÂ HDÂ 4K are achieved on an embedded NVIDIA GPU for All Intra and Random Access configurations, respectively.|