TU Berlin

Embedded Systems ArchitectureDr.-Ing. Biao Wang

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Biao Wang

Publications

GPU Parallelization of HEVC In-Loop Filters
Citation key Wang2017
Author Biao Wang and Diego F. de Souza and Mauricio Alvarez-Mesa and Chi Ching Chi and Ben Juurlink and Aleksandar Ilic and Nuno Roma and Leonel Sousa
Pages 1–21
Year 2017
ISSN 1573-7640
DOI 10.1007/s10766-017-0488-z
Journal International Journal of Parallel Programming
Abstract In the High Efficiency Video Coding (HEVC) standard, multiple decoding modules have been designed to take advantage of parallel processing. In particular, the HEVC in-loop filters (i.e., the deblocking filter and sample adaptive offset) were conceived to be exploited by parallel architectures. However, the type of the offered parallelism mostly suits the capabilities of multi-core CPUs, thus making a real challenge to efficiently exploit massively parallel architectures such as Graphic Processing Units (GPUs), mainly due to the existing data dependencies between the HEVC decoding procedures. In accordance, this paper presents a novel strategy to increase the amount of parallelism and the resulting performance of the HEVC in-loop filters on GPU devices. For this purpose, the proposed algorithm performs the HEVC filtering at frame-level and employs intrinsic GPU vector instructions. When compared to the state-of-the-art HEVC in-loop filter implementations, the proposed approach also reduces the amount of required memory transfers, thus further boosting the performance. Experimental results show that the proposed GPU in-loop filters deliver a significant improvement in decoding performance. For example, average frame rates of 76 frames per second (FPS) and 125 FPS for Ultra HD 4K are achieved on an embedded NVIDIA GPU for All Intra and Random Access configurations, respectively.
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Biography

Lupe

Biao Wang received the M.S. degree in Computer Application Technology in July 2010 and Bachelor degree in Computer Software Technology in July 2007, both from University of Electronic Science and Technology of China (UESTC), ChengDu, China. Since Oct 2010, he joined the Embedded Systems Architecture as a PhD student with scholarship from China Scholarship Council (CSC).
His research is focused on video decoding using Graphic Processing Units (GPUs). He is experienced in parallelization of H.264 and H.265 decoding kernels using OpenCL programming model. Some of these works are published in international conferences and prestigious journals.

15.05.2018: Biao Wang successfully completed his PhD defense.

Lupe

M.Sc. Biao Wang successfully completed his PhD defense on Tuesday 15th May 2018. His thesis title was: "High-performance Video Decoding using Graphics Processing Units”.
Congratulation Dr. Wang for your success and we wish you the best in your future! 

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