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SynZEN: A Hybrid TTA/VLIW Architecture with a Distributed Register File
Citation key HaMoJu2012
Author Stefan Hauser and Nico Moser and Ben Juurlink
Year 2012
ISBN 978-1-4673-2221-8
DOI 10.1109/NORCHP.2012.6403142
Journal NORCHIP
Volume 2012
Abstract The quest for higher performance within a certain power in the fields of demands unconventional architectural approaches. To this end, in this paper we present synZEN (sZ): a (micro-)architecture that combines features of very long instruction word (VLIW) and transport triggered architectures (TTAs) to cover the needs of different applications. SynZEN features a distributed register file (RF) (i.e., each functional unit (FU) has its own RF) and a wide memory connection to exploit spatial data locality. FPGA synthesis results demonstrate that due to the distributed RF the sZ design can be implemented in less area (in terms of FPGA slices) than existing TTA and VLIW designs. Furthermore, using two micro-benchmarks we show that because of the wide memory connection, sZ outperforms both the TTA as well as the VLIW design.
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