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Nexus++: a Hardware Task Management System for Multicore Systems

Summary

Since the trend of improving processor’s performance has shifted toward in- tegrating more cores on the same chip, several parallel programming models have been proposed that aim at relieving parallel programming. Examples include Google’s MapReduce, Intel’s TBB, and OmpSs.

OmpSs
is a promising approach, as it requires minimal effort of the pro- grammer to program in parallel since he or she can annotate the sequential application. The current software OmpSs runtime system, however, can be a bottleneck that limits the scalability of applications for large number of cores. Roughly speaking, the runtime system cannot compute task depen- dencies and attend to finished tasks fast enough to keep all cores busy. In this project we therefore develop Nexus++, a hardware system that provides architectural support for task-based parallel programming models such as OmpSs. The main goal of Nexus++ is to accelerate the task management responsibilities of the OmpSs runtime system.

Objectives

Nexus++
Nexus++ in a multicore system
Lupe

To develop a hardware task management system that

  • Accelerates task dependency resolution
  • Improves the performance of application with fine-grained tasks
  • Works for arbitrary task dependency graphs
  • Requires no or minimal support from the programmer.
  • Can be integrated in any type of multicore system.

Funding

This research is funded by the European Community’s Seventh Framework Programme [FP7/2007-2013] under the ENCORE Project, grant agreement n248647. It is also funded by the German-Jordanian university.

Student Projects

MSc project Design of a hardware task management unit for multicore systems, Mauricio Fayula Gonzalez.

Publications

Nexus: Hardware Support for Task-Based Programming
Citation key 10.1109/DSD.2011.62
Author Cor Meenderinck and Ben Juurlink
Pages 442-445
Year 2011
ISBN 978-0-7695-4494-6
DOI http://doi.ieeecomputersociety.org/10.1109/DSD.2011.62
Address Los Alamitos, CA, USA
Journal Digital Systems Design, Euromicro Symposium on
Publisher IEEE Computer Society
Link to publication Download Bibtex entry

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