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Inhalt des Dokuments

Sohan Lal

Kontaktdaten

Kontaktdaten
Raum:
E-N 638
Tel.:
+49 (0)30 314-22290
E-Mail
sohan [1]
Sprechstunde:
nach Vereinbarung
Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Forschung

  • LPGPU2 [2]
  • LPGPU: Low Power GPU [3]

Lehre

Lehrveranstaltungen
Advanced Computer Architectures  [4]
SS 17
Multicore Architectures (Multicore Systems) [5]
WS 16/17
Advanced Computer Architectures  [6]
SS 16
Multicore Architectures (Multicore Systems) [7]
WS 15/16
Advanced Computer Architectures  [8]
SS 15
Advanced Computer Architectures  [9]
WS 13/14
Advanced Computer Architectures  [10]
SS 2013
Advanced Computer Architectures  [11]
SS 2012

Publikationen

Sortieren nach: Autor [12]  Jahr [13]  Journal [14]

Jan Lucas and Sohan Lal and Michael Andersch and Mauricio Alvarez Mesa and Ben Juurlink (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator [15]. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS)

Jan Lucas and Sohan Lal and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2013). DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads [16]. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)

Sohan Lal and Jan Lucas and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2013). Exploring GPGPUs Workload Characteristics and Power Consumption [17]. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)

Sohan Lal and Jan Lucas and Michael Andersch and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2014). GPGPU Workload Characteristics and Performance Analysis [18]. Proc. 14th Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 115-124.

Maurice Peemen and Runbin Shi and Sohan Lal and Ben Juurlink and Bart Mesman and Henk Corporaal (2016). The Neuro Vector Engine: Flexibility to Improve Convolutional Net Efficiency for Wearable Vision [19]. Proc. Int. Conf on Design Automation, and Test in Europe,(DATE)

Sohan Lal and Jan Lucas and Ben Juurlink (2017). E²MC: Entropy Encoding based Memory Compression for GPUs [20]. Proc. 31st IEEE Int. Parallel and Distributed Processing Symposium (IPDPS)

Jan Lucas and Sohan Lal and Ben Juurlink (2018). Optimal DC/AC Data Bus Inversion Coding [21]. Proc. Int. Conf on Design Automation, and Test in Europe,(DATE)

Sohan Lal and Jan Lucas and Ben Juurlink (2018). Memory Access Granularity Aware Lossy Compression for GPUs [22]. Proc. 14th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 8)

Sohan Lal and Jan Lucas and Ben Juurlink (2019). SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs [23]. Proc. IEEE Int. Conf on Design Automation, and Test in Europe,(DATE)

Sohan Lal and Ben Juurlink (2018). A Case for Memory Access Granularity Aware Selective Lossy Compression for GPUs [24]. ACM Student Research Competition Poster and Extended Abstract at the 51st IEEE/ACM Int. Symposium on Microarchitecture (MICRO)

Biografie

Lupe [25]
© S. Lal

Sohan Lal is a postdoctoral researcher at the Technical University of Berlin (TU Berlin), working on a DFG funded research project on advanced modeling and runtime support for large-scale HPC clusters. He graduated with a Ph.D. in Computer Engineering from TU Berlin in August 2019. His dissertation was titled “Power Modeling and Architectural Techniques for Energy-Efficient GPUs” and was supervised by Prof. Ben Juurlink. At TU Berlin, he worked on two EU funded research projects on low power parallel computing on GPUs (LPGPU), where he led several tasks, collaborated with consortium members to deliver joint deliverables and contributed significantly to their success. His Ph.D. dissertation work was also conducted in the context of LPGPU projects. For his dissertation, he investigated bottlenecks that cause low performance and low energy efficiency in GPUs and proposed architectural techniques to improve performance and energy efficiency. The results of the dissertation were published in several reputed conferences such as IPDPS, DATE, ISPASS. He won several grants such as HiPEAC travel grants, a HiPEAC collaboration grant to visit Prof. Henk Coporaal (TU/e) that led to a joint publication at DATE. He was a semifinalist at ACM SRC held at MICRO'18. He is interested in computer architecture in general and graphics processing unit (GPU) architecture in particular and his broad research interests power and performance modeling, performance bottlenecks identification, memory systems, heterogeneous computing, approximate computing, applied machine learning, and GPU security.

Before Ph.D., he received his masters from the Indian Institute of Technology, Delhi (IITD) in 2011. Before that, he worked as a Lecturer at Shri Mata Vaishno Devi University, which was the first teaching stint that made him deeply passionate and excited about teaching and mentorship. He also worked as an IT specialist in the Government of India. He received his bachelor in Computer Science and Engineering from Government College of Engineering and Technology (GCET), Jammu, India in 2003.

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