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Sohan Lal


E-N 638
+49 (0)30 314-22290
sohan [1]
nach Vereinbarung
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin


  • LPGPU2 [2]
  • LPGPU: Low Power GPU [3]


Advanced Computer Architectures  [4]
SS 17
Multicore Architectures (Multicore Systems) [5]
WS 16/17
Advanced Computer Architectures  [6]
SS 16
Multicore Architectures (Multicore Systems) [7]
WS 15/16
Advanced Computer Architectures  [8]
SS 15
Advanced Computer Architectures  [9]
WS 13/14
Advanced Computer Architectures  [10]
SS 2013
Advanced Computer Architectures  [11]
SS 2012


SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs
Zitatschlüssel Lal2019:DATE
Autor Sohan Lal and Jan Lucas and Ben Juurlink
Buchtitel Proc. IEEE Int. Conf on Design Automation, and Test in Europe,(DATE)
Jahr 2019
Download Bibtex Eintrag [12]


Lupe [14]

Sohan Lal is a postdoctoral researcher at the Technical University of Berlin (TU Berlin), working on a DFG funded research project on advanced modeling and runtime support for large-scale HPC clusters. He graduated with a Ph.D. in Computer Engineering from TU Berlin in August 2019. His dissertation was titled “Power Modeling and Architectural Techniques for Energy-Efficient GPUs” and was supervised by Prof. Ben Juurlink. At TU Berlin, he worked on two EU funded research projects on low power parallel computing on GPUs (LPGPU), where he led several tasks, collaborated with consortium members to deliver joint deliverables and contributed significantly to their success. His Ph.D. dissertation work was also conducted in the context of LPGPU projects. For his dissertation, he investigated bottlenecks that cause low performance and low energy efficiency in GPUs and proposed architectural techniques to improve performance and energy efficiency. The results of the dissertation were published in several reputed conferences such as IPDPS, DATE, ISPASS. He won several grants such as HiPEAC travel grants, a HiPEAC collaboration grant to visit Prof. Henk Coporaal (TU/e) that led to a joint publication at DATE. He was a semifinalist at ACM SRC held at MICRO'18. He is interested in computer architecture in general and graphics processing unit (GPU) architecture in particular and his broad research interests power and performance modeling, performance bottlenecks identification, memory systems, heterogeneous computing, approximate computing, applied machine learning, and GPU security.

Before Ph.D., he received his masters from the Indian Institute of Technology, Delhi (IITD) in 2011. Before that, he worked as a Lecturer at Shri Mata Vaishno Devi University, which was the first teaching stint that made him deeply passionate and excited about teaching and mentorship. He also worked as an IT specialist in the Government of India. He received his bachelor in Computer Science and Engineering from Government College of Engineering and Technology (GCET), Jammu, India in 2003.

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