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TU Berlin

Inhalt des Dokuments

Gabriel Luca Nazar

Kontaktdaten

Kontaktdaten
Raum:
E-N 638
Tel.:
+49 (0)30 314-22290
E-Mail

Sprechstunde:
nach Vereinbarung

Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Forschung

  • Computer architecture
  • Reconfigurable systems
  • High-level synthesis
  • Approximate computing
  • Fault tolerance

Veröffentlichungen

  • https://doi.org/10.1109/COMST.2019.2943690 G. S. Niemiec, L. M. S. Batista, A. E. Schaeffer-Filho and G. L. Nazar, "A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions," in IEEE Communications Surveys & Tutorials, vol. 22, no. 1, pp. 504-525, Firstquarter 2020.
  • http://dx.doi.org/10.1145/3358182 Marcos T. Leipnitz and Gabriel L. Nazar. 2019. High-Level Synthesis of Approximate Designs under Real-Time Constraints. ACM Trans. Embed. Comput. Syst. 18, 5s, Article 59 (October 2019), 21 pages
  • http://dx.doi.org/10.1016/j.microrel.2019.113406 D.M. Cardoso, R. Tonetto, M. Brandalero, G. Nazar, A.C. Beck, J.R. Azambuja, "Exploring the limitations of dataflow SIHFT techniques in out-of-order superscalar processors," Microelectronics Reliability, Volumes 100–101, 2019
  • https://doi.org/10.1109/IOLTS.2019.8854457 E. N. d. Souza and G. L. Nazar, "Cost-effective Resilient FPGA-based LDPC Decoder Architecture," 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, 2019, pp. 84-89.
  • https://doi.org/10.1145/3316781.3317839 Marcos T. Leipnitz and Gabriel L. Nazar. 2019. High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs. In Proceedings of the 56th Annual Design Automation Conference 2019 (DAC ’19). Association for Computing Machinery, New York, NY, USA, Article 126, 1–6.
  • https://doi.org/10.1109/VLSI-SoC.2019.8920350 R. B. Tonetto, D. M. Cardoso, M. Brandalero, L. Agostini, G. L. Nazar, J. R. Azambuja, and A. C. S. Beck, "A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors," 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Cuzco, Peru, 2019, pp. 287-292.
  • https://doi.org/10.1109/ICECS46596.2019.8964749 D. M. Cardoso, R. B. Tonetto, M. Brandalero, L. Agostini, G. L. Nazar, J. R. Azambuja, and A. C. S. Beck, "Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors," 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genoa, Italy, 2019, pp. 201-204.
  • http://dx.doi.org/10.1145/3144533 Leonardo Pereira-Santos, Gabriel Luca Nazar, and Luigi Carro. 2018. Repair of FPGA-Based Real-Time Systems With Variable Slacks. ACM Trans. Des. Autom. Electron. Syst. 23, 2, Article 19 (January 2018), 20 pages.
  • http://dx.doi.org/10.1007/s10836-018-5736-7 Leipnitz, M.T., Nazar, G.L. Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching. J Electron Test 34, 487–506 (2018).
  • https://doi.org/10.23919/DATE.2018.8342082 R. B. Tonetto, G. L. Nazar and A. C. S. Beck, "Precise evaluation of the fault sensitivity of OoO superscalar processors," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 613-616.
  • http://dx.doi.org/10.1016/j.micpro.2017.05.002 Leonardo Pereira-Santos, Gabriel L. Nazar, Luigi Carro, "Exploring redundancy granularities to repair real-time FPGA-based systems," Microprocessors and Microsystems, Volume 51, 2017, Pages 264-274.
  • https://doi.org/10.23919/DATE.2017.7927018 T. Jost, G. Nazar and L. Carro, "An energy-efficient memory hierarchy for multi-issue processors," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 368-373.

Lehre

Lehrveranstaltungen
AES Bachelor Seminar
SS 2020

Zusatzinformationen / Extras

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