TU Berlin

Architektur eingebetteter SystemeÁlvarez Mesa, Mauricio

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Mauricio Álvarez Mesa

Kontaktdaten

Kontaktdaten
Raum:
E-N 601/602
Tel.:
+49 (0)30 314-21357
Fax:
+49 (0)30 314-22943
E-Mail

Sprechstunde:
nach Vereinbarung
Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Lehre

Lehrveranstaltungen
Advanced Computer Architectures 
SS 2013

Publikationen

Azevedo, A., Juurlink, B., Meenderinck, C., Terechko, A., Hoogerbrugge, J., Mesa, M. A., Ramírez, A. and Valero, M. (2011). A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers IV. Springer Berlin Heidelberg, 111-134.


Sanz-Rodríguez, S., Alvarez-Mesa, M., Mayer, T. and Schierl, T. (2015). A Parallel H.264/SVC Encoder for High Definition Video Conferencing. Signal Processing: Image Communication, 89 - 106.


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilić, A., Roma, N. and Sousa, L. (2018). Highly Parallel HEVC Decoding for Heterogeneous Systems with CPU and GPU. Signal Processing: Image Communication


Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M. A., Sanchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. and Gaydadjiev, G. (2010). The SARC Architecture. Micro, IEEE, 16 -29.


Chi, C. C., Alvarez-Mesa, M., Lucas, J., Juurlink, B. and Schierl, T. (2013). Parallel HEVC Decoding on Multi- and Many-core Architectures. A Power and Performance Analysis.. Journal of Signal Processing Systems


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilic, A., Roma, N. and Sousa, L. (2017). GPU Parallelization of HEVC In-Loop Filters. International Journal of Parallel Programming, 1–21.


Chi, C. C., Mesa, M. A., Juurlink, B., Clare, G., Henry, F., Pateux, S. and Schierl, T. (2012). Parallel Scalability and Efficiency of HEVC Parallelization Approaches. IEEE Transactions on Circuits and Systems for Video Technology


Wang, B., Alvarez-Mesa, M., Chi, C. C. and Juurlink, B. (2015). Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL. IEEE Transactions on Circuits and Systems for Video Technology, 525-531.


Chi, C. C., Alvarez-Mesa, M., Bross, B., Juurlink, B. and Schierl, T. (2015). SIMD Acceleration for HEVC Decoding. IEEE Transactions on Circuits and Systems for Video Technology, 841-855.


Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2015). Low-Power High-Efficiency Video Decoding Using General-Purpose Processors. ACM Transaction on Architecture and Code Optimization. ACM, 56:1–56:25.


Lucas, J., Andersch, M., Alvarez-Mesa, M. and Juurlink, B. (2015). Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency. ACM Trans. Archit. Code Optim.. ACM, 32:1–32:26.


Lucas, J., Lal, S., Andersch, M., Mesa, M. A. and Juurlink, B. (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS)


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Application-specific Cache and Prefetching for HEVC CABAC Decoding. IEEE Multimedia, Volume 24, Issue 1, Jan.-Mar. 2017, 72-85.


Sanz-Rodríguez, S., Mayer, T., Alvarez-Mesa, M. and Schierl, T. (2013). A Low-Complexity Parallel-Friendly Rate Control Algorithm for Ultra-Low Delay High Definition Video Coding. Multimedia and Expo Workshops (ICMEW), 2013 IEEE International Conference on, 1-4.


Wang, B., Alvarez-Mesa, M., Chi, C. C. and Juurlink, B. (2013). An Optimized Parallel IDCT on Graphics Processing Units. Euro-Par 2012: Parallel Processing Workshops. Springer Berlin Heidelberg, 155-164.


Biografie

Lupe

Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.

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