TU Berlin

Architektur eingebetteter SystemeÁlvarez Mesa, Mauricio

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Mauricio Álvarez Mesa

Kontaktdaten

Kontaktdaten
Raum:
E-N 601/602
Tel.:
+49 (0)30 314-21357
Fax:
+49 (0)30 314-22943
E-Mail

Sprechstunde:
nach Vereinbarung
Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Lehre

Lehrveranstaltungen
Advanced Computer Architectures 
SS 2013

Publikationen

Wang, B., Alvarez-Mesa, M., Chi, C. C. and Juurlink, B. (2015). Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL. IEEE Transactions on Circuits and Systems for Video Technology, 525-531.


Wang, B., Alvarez-Mesa, M., Chi, C. C. and Juurlink, B. (2013). An Optimized Parallel IDCT on Graphics Processing Units. Euro-Par 2012: Parallel Processing Workshops. Springer Berlin Heidelberg, 155-164.


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilić, A., Roma, N. and Sousa, L. (2018). Highly Parallel HEVC Decoding for Heterogeneous Systems with CPU and GPU. Signal Processing: Image Communication


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilic, A., Roma, N. and Sousa, L. (2017). GPU Parallelization of HEVC In-Loop Filters. International Journal of Parallel Programming, 1–21.


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilic, A., Roma, N. and Sousa, L. (2016). Efficient HEVC decoder for heterogeneous CPU with GPU systems. 2016 IEEE 18th International Workshop on Multimedia Signal Processing (MMSP), 1-6.


Sanz-Rodríguez, S., Mayer, T., Alvarez-Mesa, M. and Schierl, T. (2013). A Low-Complexity Parallel-Friendly Rate Control Algorithm for Ultra-Low Delay High Definition Video Coding. Multimedia and Expo Workshops (ICMEW), 2013 IEEE International Conference on, 1-4.


Sanz-Rodríguez, S., Alvarez-Mesa, M., Mayer, T. and Schierl, T. (2015). A Parallel H.264/SVC Encoder for High Definition Video Conferencing. Signal Processing: Image Communication, 89 - 106.


Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M. A., Sanchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. and Gaydadjiev, G. (2010). The SARC Architecture. Micro, IEEE, 16 -29.


Pohl, A., Cosenza, B., Mesa, M. A., Chi, C. C. and Juurlink, B. H. H. (2016). An evaluation of current SIMD programming models for C++. Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector Processing, WPMVP@PPoPP 2016, Barcelona, Spain, March 13, 2016, 3:1–3:8.


Philipp Habermann, C. C. C. M. A.-M. B. J. (2015). Optimizing HEVC CABAC Decoding with a Context Model Cache and Application-specific Prefetching. Proceedings of the 11th IEEE International Symposium on Multimedia (ISM 2015), 429-434.


Mesa, M. A., Chi, C. C., Juurlink, B., George, V. and Schierl, T. (2012). Parallel Video Decoding in the Emerging HEVC Standard. Proceedings of the 37th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2012


Marquez, G. C., Chi, C. C., Martinez, J. L., Cuenca, P., Mesa, M. A., Sanz-Rodriguez, S. and Juurlink, B. (2015). Reducing HEVC Encoding Complexity Using Two-Stage Motion Estimation. Visual Communications and Image Processing, VCIP


Lucas, J., Lal, S., Andersch, M., Mesa, M. A. and Juurlink, B. (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS)


Lucas, J., Alvarez-Mesa, M., Andersch, M. and Juurlink, B. (2014). Sparkk: Quality-Scalable Approximate Storage in DRAM. The Memory Forum


Lucas, J., Lal, S., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2013). DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)


Biografie

Lupe

Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.

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