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TU Berlin

Inhalt des Dokuments

Mauricio Álvarez Mesa


E-N 601/602
+49 (0)30 314-21357
+49 (0)30 314-22943

nach Vereinbarung
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin


Advanced Computer Architectures 
SS 2013


Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M. A., Sanchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. and Gaydadjiev, G. (2010). The SARC Architecture. Micro, IEEE, 16 -29.

Azevedo, A., Juurlink, B., Meenderinck, C., Terechko, A., Hoogerbrugge, J., Mesa, M. A., Ramírez, A. and Valero, M. (2011). A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers IV. Springer Berlin Heidelberg, 111-134.

Juurlink, B., Alvarez-Mesa, M., Chi, C. C., Azevedo, A., Meenderinck, C. and Ramirez, A. (2012). Scalable Parallel Programming Applied to H.264/AVC Decoding. Springer.

Mesa, M. A., Chi, C. C., Juurlink, B., George, V. and Schierl, T. (2012). Parallel Video Decoding in the Emerging HEVC Standard. Proceedings of the 37th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2012

Chi, C. C., Mesa, M. A., Juurlink, B., Clare, G., Henry, F., Pateux, S. and Schierl, T. (2012). Parallel Scalability and Efficiency of HEVC Parallelization Approaches. IEEE Transactions on Circuits and Systems for Video Technology

Wang, B., Alvarez-Mesa, M., Chi, C. C. and Juurlink, B. (2013). An Optimized Parallel IDCT on Graphics Processing Units. Euro-Par 2012: Parallel Processing Workshops. Springer Berlin Heidelberg, 155-164.

Chi, C. C., Alvarez-Mesa, M., Lucas, J., Juurlink, B. and Schierl, T. (2013). Parallel HEVC Decoding on Multi- and Many-core Architectures. A Power and Performance Analysis.. Journal of Signal Processing Systems

Lucas, J., Lal, S., Andersch, M., Mesa, M. A. and Juurlink, B. (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS)

Sanz-Rodríguez, S., Mayer, T., Alvarez-Mesa, M. and Schierl, T. (2013). A Low-Complexity Parallel-Friendly Rate Control Algorithm for Ultra-Low Delay High Definition Video Coding. Multimedia and Expo Workshops (ICMEW), 2013 IEEE International Conference on, 1-4.

Lucas, J., Lal, S., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2013). DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)

Lal, S., Lucas, J., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2013). Exploring GPGPUs Workload Characteristics and Power Consumption. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)

Bross, B., Alvarez-Mesa, M., George, V., Chi, C. C., Mayer, T., Juurlink, B. and Schierl, T. (2013). HEVC Real-time Decoding. Proc. SPIE. Applications of Digital Image Processing XXXVI, 88561R-88561R-11.

Bross, B., George, V., Alvarez-Mesa, M., Mayer, T., Chi, C. C., Brandenburg, J., Schierl, T., Marpe, D. and Juurlink, B. (2013). HEVC Performance and Complexity for 4K Video. Proc. Third IEEE Int. Conf. on Consumer Electronics - Berlin (ICCE-Berlin), 44-47.

Chi, C. C., Mesa, M. A., Juurlink, B., George, V. and Schierl, T. (2013). Improving the Parallelization Efficiency of HEVC Decoding. Proceedings of the 2012 International Conference on Image Processing (ICIP)

Lucas, J., Alvarez-Mesa, M., Andersch, M. and Juurlink, B. (2014). Sparkk: Quality-Scalable Approximate Storage in DRAM. The Memory Forum



Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.

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