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TU Berlin

Inhalt des Dokuments

Mauricio Álvarez Mesa

Kontaktdaten

Kontaktdaten
Raum:
E-N 601/602
Tel.:
+49 (0)30 314-21357
Fax:
+49 (0)30 314-22943
E-Mail

Sprechstunde:
nach Vereinbarung
Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Lehre

Lehrveranstaltungen
Advanced Computer Architectures 
SS 2013

Publikationen

Lucas, J., Andersch, M., Alvarez-Mesa, M. and Juurlink, B. (2015). Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency. ACM Trans. Archit. Code Optim.. ACM, 32:1–32:26.


Lal, S., Lucas, J., Andersch, M., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2014). GPGPU Workload Characteristics and Performance Analysis. Proc. 14th Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 115-124.


Lal, S., Lucas, J., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2013). Exploring GPGPUs Workload Characteristics and Power Consumption. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)


Juurlink, B., Alvarez-Mesa, M., Chi, C. C., Azevedo, A., Meenderinck, C. and Ramirez, A. (2012). Scalable Parallel Programming Applied to H.264/AVC Decoding. Springer.


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Application-specific Cache and Prefetching for HEVC CABAC Decoding. IEEE Multimedia, Volume 24, Issue 1, Jan.-Mar. 2017, 72-85.


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Improved Wavefront Parallel Processing for HEVC Decoding. Proceedings of the 13th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2017), 253-256.


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Syntax Element Partitioning for high-throughput HEVC CABAC Decoding. Proceedings of the 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2017), 1308-1312.


Göbel, M., Elhossini, A., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). A Quantitative Analysis of the Memory Architecture of FPGA-SoCs. Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC 2017). Best Paper Award winner.


Göbel, M., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2015). High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis. Proceedings of the 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2015). HiPEAC Paper Award.


Chi, C. C., Mesa, M. A., Juurlink, B., Clare, G., Henry, F., Pateux, S. and Schierl, T. (2012). Parallel Scalability and Efficiency of HEVC Parallelization Approaches. IEEE Transactions on Circuits and Systems for Video Technology


Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2015). Low-Power High-Efficiency Video Decoding Using General-Purpose Processors. ACM Transaction on Architecture and Code Optimization. ACM, 56:1–56:25.


Chi, C. C., Alvarez-Mesa, M., Bross, B., Juurlink, B. and Schierl, T. (2015). SIMD Acceleration for HEVC Decoding. IEEE Transactions on Circuits and Systems for Video Technology, 841-855.


Chi, C. C., Alvarez-Mesa, M., Lucas, J., Juurlink, B. and Schierl, T. (2013). Parallel HEVC Decoding on Multi- and Many-core Architectures. A Power and Performance Analysis.. Journal of Signal Processing Systems


Chi, C. C., Mesa, M. A., Juurlink, B., George, V. and Schierl, T. (2013). Improving the Parallelization Efficiency of HEVC Decoding. Proceedings of the 2012 International Conference on Image Processing (ICIP)


Castrillón, J., Thiele, L., Schor, L., Sheng, W., Juurlink, B. H. H., Mesa, M. A., Pohl, A., Jessenberger, R., Reyes, V. and Leupers, R. (2015). Multi/many-core programming: where are we standing?. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 1708–1717.


Biografie

Lupe

Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.

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