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TU Berlin

Inhalt des Dokuments

Mauricio Álvarez Mesa

Kontaktdaten

Kontaktdaten
Raum:
E-N 601/602
Tel.:
+49 (0)30 314-21357
Fax:
+49 (0)30 314-22943
E-Mail
alvarez [1]
Sprechstunde:
nach Vereinbarung
Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Forschung

  • LPGPU: Low Power GPU [2]
  • High performance video coding [3]
  • Film265 [4]

Lehre

Lehrveranstaltungen
Advanced Computer Architectures  [5]
SS 2013

Publikationen

vor >> [8]

Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M. A., Sanchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. and Gaydadjiev, G. (2010). The SARC Architecture [12]. Micro, IEEE, 16 -29.


Azevedo, A., Juurlink, B., Meenderinck, C., Terechko, A., Hoogerbrugge, J., Mesa, M. A., Ramírez, A. and Valero, M. (2011). A Highly Scalable Parallel Implementation of H.264 [13]. Transactions on High-Performance Embedded Architectures and Compilers IV. Springer Berlin Heidelberg, 111-134.


Mesa, M. A., Chi, C. C., Juurlink, B., George, V. and Schierl, T. (2012). Parallel Video Decoding in the Emerging HEVC Standard [14]. Proceedings of the 37th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2012


Chi, C. C., Mesa, M. A., Juurlink, B., George, V. and Schierl, T. (2013). Improving the Parallelization Efficiency of HEVC Decoding [15]. Proceedings of the 2012 International Conference on Image Processing (ICIP)


Juurlink, B., Alvarez-Mesa, M., Chi, C. C., Azevedo, A., Meenderinck, C. and Ramirez, A. (2012). Scalable Parallel Programming Applied to H.264/AVC Decoding [16]. Springer.


Chi, C. C., Alvarez-Mesa, M., Lucas, J., Juurlink, B. and Schierl, T. (2013). Parallel HEVC Decoding on Multi- and Many-core Architectures. A Power and Performance Analysis. [17]. Journal of Signal Processing Systems


Chi, C. C., Mesa, M. A., Juurlink, B., Clare, G., Henry, F., Pateux, S. and Schierl, T. (2012). Parallel Scalability and Efficiency of HEVC Parallelization Approaches [18]. IEEE Transactions on Circuits and Systems for Video Technology


Lucas, J., Lal, S., Andersch, M., Mesa, M. A. and Juurlink, B. (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator [19]. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS)


Bross, B., Alvarez-Mesa, M., George, V., Chi, C. C., Mayer, T., Juurlink, B. and Schierl, T. (2013). HEVC Real-time Decoding [20]. Proc. SPIE. Applications of Digital Image Processing XXXVI, 88561R-88561R-11.


Bross, B., George, V., Alvarez-Mesa, M., Mayer, T., Chi, C. C., Brandenburg, J., Schierl, T., Marpe, D. and Juurlink, B. (2013). HEVC Performance and Complexity for 4K Video [21]. Proc. Third IEEE Int. Conf. on Consumer Electronics - Berlin (ICCE-Berlin), 44-47.


Lucas, J., Lal, S., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2013). DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads [22]. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)


Lal, S., Lucas, J., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2013). Exploring GPGPUs Workload Characteristics and Power Consumption [23]. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)


Lucas, J., Alvarez-Mesa, M., Andersch, M. and Juurlink, B. (2014). Sparkk: Quality-Scalable Approximate Storage in DRAM [24]. The Memory Forum


Lal, S., Lucas, J., Andersch, M., Alvarez-Mesa, M., Elhossini, A. and Juurlink, B. (2014). GPGPU Workload Characteristics and Performance Analysis [25]. Proc. 14th Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 115-124.


Andersch, M., Lucas, J., Alvarez-Mesa, M. and Juurlink, B. (2014). Analyzing GPGPU Pipeline Latency [26]. Proc. 10th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 14)


vor >> [29]

Biografie

Lupe [30]

Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.

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