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TU Berlin

Inhalt des Dokuments

Mauricio Álvarez Mesa

Kontaktdaten

Kontaktdaten
Raum:
E-N 601/602
Tel.:
+49 (0)30 314-21357
Fax:
+49 (0)30 314-22943
E-Mail

Sprechstunde:
nach Vereinbarung
Anschrift:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Lehre

Lehrveranstaltungen
Advanced Computer Architectures 
SS 2013

Publikationen

Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilić, A., Roma, N. and Sousa, L. (2018). Highly Parallel HEVC Decoding for Heterogeneous Systems with CPU and GPU. Signal Processing: Image Communication


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Application-specific Cache and Prefetching for HEVC CABAC Decoding. IEEE Multimedia, Volume 24, Issue 1, Jan.-Mar. 2017, 72-85.


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Improved Wavefront Parallel Processing for HEVC Decoding. Proceedings of the 13th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2017), 253-256.


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilic, A., Roma, N. and Sousa, L. (2017). GPU Parallelization of HEVC In-Loop Filters. International Journal of Parallel Programming, 1–21.


Habermann, P., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). Syntax Element Partitioning for high-throughput HEVC CABAC Decoding. Proceedings of the 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2017), 1308-1312.


Göbel, M., Elhossini, A., Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2017). A Quantitative Analysis of the Memory Architecture of FPGA-SoCs. Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC 2017). Best Paper Award winner.


Wang, B., Souza, D. F. d., Alvarez-Mesa, M., Chi, C. C., Juurlink, B., Ilic, A., Roma, N. and Sousa, L. (2016). Efficient HEVC decoder for heterogeneous CPU with GPU systems. 2016 IEEE 18th International Workshop on Multimedia Signal Processing (MMSP), 1-6.


Pohl, A., Cosenza, B., Mesa, M. A., Chi, C. C. and Juurlink, B. H. H. (2016). An evaluation of current SIMD programming models for C++. Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector Processing, WPMVP@PPoPP 2016, Barcelona, Spain, March 13, 2016, 3:1–3:8.


Chi, C. C., Alvarez-Mesa, M., Bross, B., Juurlink, B. and Schierl, T. (2015). SIMD Acceleration for HEVC Decoding. IEEE Transactions on Circuits and Systems for Video Technology, 841-855.


Wang, B., Alvarez-Mesa, M., Chi, C. C. and Juurlink, B. (2015). Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL. IEEE Transactions on Circuits and Systems for Video Technology, 525-531.


Andersch, M., Lucas, J., Alvarez-Mesa, M. and Juurlink, B. (2015). On Latency in GPU Throughput Microarchitectures. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS), 169-170.


Chi, C. C., Alvarez-Mesa, M. and Juurlink, B. (2015). Low-Power High-Efficiency Video Decoding Using General-Purpose Processors. ACM Transaction on Architecture and Code Optimization. ACM, 56:1–56:25.


Sanz-Rodríguez, S., Alvarez-Mesa, M., Mayer, T. and Schierl, T. (2015). A Parallel H.264/SVC Encoder for High Definition Video Conferencing. Signal Processing: Image Communication, 89 - 106.


Marquez, G. C., Chi, C. C., Martinez, J. L., Cuenca, P., Mesa, M. A., Sanz-Rodriguez, S. and Juurlink, B. (2015). Reducing HEVC Encoding Complexity Using Two-Stage Motion Estimation. Visual Communications and Image Processing, VCIP


Lucas, J., Andersch, M., Alvarez-Mesa, M. and Juurlink, B. (2015). Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency. ACM Trans. Archit. Code Optim.. ACM, 32:1–32:26.


Biografie

Lupe

Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.

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