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Welcome at AES


The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.


18.07.2019: AES Paper Accepted at IESS 2019


The paper "An Efficient Lightweight Framework for Porting Vision Algorithms on Embedded SoCs" by Apurv Ashish, Sohan Lal and Ben Juurlink has been accepted for publication at the 6th International Embedded Systems Symposium (IESS). The authors propose a novel lightweight framework for porting computer vision algorithms on embedded platforms which addresses the drawbacks of the existing BAM framework.

The 6th edition of IESS will take place from Sep 9-11, 2019 in Friedrichshafen, Germany. More information can be found at http://www.iess.org/

10.07.2019: AES Paper Accepted at MASCOTS 2019


The AES paper "Portable Cost Modeling for Auto-Vectorizers", authored by Angela Pohl, Biagio Cosenza, and Ben Juurlink, has been accepted for publication at the 27th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). The paper proposes a more accurate cost model for auto-vectorizing compilers to reduce mispredictions during their optimization stages and enable the comparison of different optimization options within the compiler.

MASCOTS will take place in Rennes, France from October 22nd to 25th. All papers will be available for open preview free of charge between September 20th and October 28th!

27.05.2019: MEMPower power model presented at ARCS 2019.


Jan Lucas presented the MEMPower model at ARCS 2019. MEMPower is a detailed empirical power model for GPU memory access. It models the data dependent energy consumption as well as individual core specific differences. We explain how the model was calibrated using special micro benchmarks as well as a high-resolution power measurement testbed. A novel technique to identify the number of memory channels and the memory channel of a specific address is presented. Our results show significant differences in the access energy of specific GPU cores, while the access energy of the different memory channels from the same GPU cores is almost identical. MEMPower is able to model these differences and provide good predictions of the access energy for specific memory accesses.

More information can be found at http://arcs2019.itec.kit.edu/. The paper can be downloaded as OpenAccess at 


21.05.2019: AES paper accepted for publication at ICPP 2019.


The paper "Predictable GPU Frequency Scaling for Energy and Performance" by AES members Kaijie Fan, Dr. Biagio Cosenza and Prof. Dr. Ben Juurlink has been accepted for publication at the 48th International Conference on Parallel Processing (ICPP). The paper proposes a method to predict the best core and memory frequency configurations on GPUs for a new OpenCL kernel without executing it.

ICPP is one of the oldest continuously running computer science conferences in parallel computing in the world. The 48th ICPP will be held in Kyoto, Japan on August 5-8, 2019.

For more information please visit: https://www.hpcs.cs.tsukuba.ac.jp/icpp2019/

20.05.2019: Four AES Papers Accepted at HPCS 2019.


Four AES papers have been accepted at the 2019 International Conference on High Performance Computing & Simulation (HPCS 2019) which is held in Dublin, Ireland from July 15-19. They showcase the broad variety of research conducted in the AES group:

  • A Performance Analysis of Vector Length Agnostic Code by Angela Pohl, Mirko Greese, Biagio Cosenza, Ben Juurlink
  • Performance Counters based Power Modeling of Mobile GPUs using Deep Learning by Nadjib Mammeri, Markus Neu, Sohan Lal, Ben Juurlink
  • Approximating Memory-bound Applications on Mobile GPUs by Daniel Maier, Nadjib Mammeri, Biagio Cosenza, Ben Juurlink
  • Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC by Matthias Goebel, Kai Norman Clasen, Robert Drehmel and Ben Juurlink 

Under the theme of “HPC and Modeling & Simulation for the 21st Century," HPCS 2019 will focus on a wide range of the state-of-the-art as well as emerging topics pertaining to high performance and large scale computing systems at both the client and backend levels.

24.04.2009: Kaijie Fan Receives Student Grant for ACACES 2019.


Kaijie Fan has been admitted with student grant to attend the "Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2019). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.                                                                                          
ACACES 2019 will take place in Fiuggi, Italy, from July 14th to July 20th, 2019.                                                                                                                                                  
For more information please visit: http://acaces.hipeac.net/2019/

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