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Inhalt des Dokuments

Willkommen bei AES

Lupe

Das Fachgebiet Architektur Eingebetteter Systeme (AES) beschäftigt sich in Forschung und Lehre mit allen Bereichen der Rechnerarchitektur, von energieeffizienten Systemen bis hin zu massiv parallelen Hochleistungsrechnern. Dabei liegt der Schwerpunkt auf dem Entwurf und der Implementierung von hochperformanten eingebetteten Systemen, bei denen Anwendungsanforderungen mit neuartigen Architekturen optimal in Einklang gebracht werden sollen. Zusätzlich befassen wir uns mit der Verbesserung von Energieeffizienz, Programmierbarkeit, Vorhersagbarkeit und Fehlertoleranz moderner Prozessorarchitekturen.

News

07.12.2018, 10:15h: Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?. Prof. Dr. Henk Corporaal.

Lupe
  • Title: Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?
  • Presenter: Prof. Dr. Henk Corporaal (TU Eindhoven, Netherlands)
  • Date and time: Thursday December 7, 2018 - 10:15h
  • Room: EN 644

Deep Learning and Convolutional Neural Networks (CNNs) have revolutionized important domains like machine learning and computer vision. The huge success of deep learning accelerates research in that particular domain and thereby the complexity and diversity of state-of-the-art network models has increased significantly. This opens several challenges for CNN accelerator designers.During this presentation we will go over the state-of-the-art networks and accelerator solutions. We will present our view on compute efficiency and flexibility. We demonstrate that the well-known optimization techniques form the computing industry are key to improve efficiency. We present a holistic approach that improves efficiency by algorithmic optimizations, data reuse improvements, custom accelerators, and the less obvious but very important challenges in code generation.

22.11.2018, 10:15h: Talk: Two Roads to Parallelism: Compilers and Libraries, Prof. Dr. Lawrence Rauchwerger (Texas A&M University, USA), Room: EN 644.

Lupe
  • Title: Two Roads to Parallelism: Compilers and Libraries
  • Presenter: Prof. Dr. Lawrence Rauchwerger (Texas A&M University, USA)
  • Date: November 22, 2018
  • Time: 10:15
  • Room: EN 644

Parallel computers have come of age and need parallel software to justify their usefulness. There are two major avenues to get  programs to run in parallel: parallelizing compilers and parallel languages and/or libraries. In this talk we present our latest results  using both approaches and draw some conclusions about their relative effectiveness and potential. n the first part we introduce the Hybrid Analysis (HA) compiler framework that can seamlessly integrate static and run-time analysis of memory references into a single framework capable of full automatic loop level parallelization. Experimental results on 26 benchmarks show full program speedups superior to those obtained by the Intel Fortran compilers. In the second part of this talk we present the Standard Template Adaptive Parallel Library (STAPL) based approach to parallelizing code. STAPL is a collection of generic data structures and algorithms that provides a high productivity, parallel programming infrastructure analogous to the C++ Standard Template Library (STL). In this talk, we provide an overview of the major STAPL components with particular emphasis on graph algorithms. We then present scalability results of real codes using peta scale machines such as IBM BG/Q and Cray. Finally we present some of our ideas for future work in this area.

09.11.2018: AES paper accepted at DATE 2019.

Lupe

The paper "SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs" by Sohan Lal, Jan Lucas, and Ben Juurlink has been accepted for publication at DATE 2019 with a long presentation. The paper proposes a novel memory access granularity aware selective approximation which intelligently trades small accuracy for a higher performance.

DATE is the top scientific event in Design, Automation, and Test of microelectronics and embedded systems for the academic and industrial research communities worldwide. The 2019 edition of the conference will take place from March 25-29 in Florence, Italy. More information can be found at https://www.date-conference.com/ 

07.11.2018: Vorlesung Rechnerorganisation hat begonnen

Lupe

Die Vorlesung Rechnerorganisation hat mit mehr als 1100 Anmeldungen begonnen! Im Rahmen dieser Veranstaltung lernen Studierende aus den Studiengängen Informatik, Technische Informatik, Medieninformatik und des Wirtschaftsingenieurwesens die grundlegende Technologien und Komponenten einer Rechnerarchitektur kennen. Sie befassen sich u.a. mit der Zahlendarstellung und Rechnerarithmetik, Leistung  und der Programmierung in Maschinensprache und Assembler.

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Leiter

Prof. Dr. Ben Juurlink
+49.30.314-73130/73131
Raum E-N 642

Sekretariat

Sara Tennstedt
Sekr. EN 12
Raum E-N 645
Tel. +49.30.314-73130

Öffnungszeiten:
Di 10-12, Do 12-14
und nach Vereinbarung

Postanschrift

Technische Universität Berlin
Architektur eingebetteter Systeme
Sekr. EN 12
Einsteinufer 17 -6. OG
10587 Berlin