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Willkommen bei AES

Lupe

Das Fachgebiet Architektur Eingebetteter Systeme (AES) beschäftigt sich in Forschung und Lehre mit allen Bereichen der Rechnerarchitektur, von energieeffizienten Systemen bis hin zu massiv parallelen Hochleistungsrechnern. Dabei liegt der Schwerpunkt auf dem Entwurf und der Implementierung von hochperformanten eingebetteten Systemen, bei denen Anwendungsanforderungen mit neuartigen Architekturen optimal in Einklang gebracht werden sollen. Zusätzlich befassen wir uns mit der Verbesserung von Energieeffizienz, Programmierbarkeit, Vorhersagbarkeit und Fehlertoleranz moderner Prozessorarchitekturen.

News

01.08.2019: Sohan Lal Successfully Defended his PhD.

Lupe

Sohan Lal successfully defended his Ph.D. thesis titled "Power Modeling and Architectural Techniques for Energy-Efficient GPUs" on August 1. Congratulations Dr. Lal for your success and we wish you the best for your future!

19.07.2019: AES Papers Stand Out at HPCS 2019.

Daniel Maier with Outstanding Paper Runner Up Award
Lupe

HPCS 2019 is currently taking place in Dublin, Ireland. Four AES papers are presented at the conference by Angela Pohl, Nadjib Mammeri, Daniel Maier and Matthias Goebel. The last two papers being also nominated for the Outstanding Paper Award.

  • A Performance Analysis of Vector Length Agnostic Code Angela Pohl, Mirko Greese, Biagio Cosenza, Ben Juurlink
  • Performance Counters based Power Modeling of Mobile GPUs using Deep Learning Nadjib Mammeri, Markus Neu, Sohan Lal, Ben Juurlink
  • Approximating Memory-bound Applications on Mobile GPUs by Daniel Maier, Nadjib Mammeri, Biagio Cosenza, Ben Juurlink
  • Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC by Matthias Goebel, Kai Norman Clasen, Robert Drehmel, Ben Juurlink

At Wednesday night's banquet the paper by Daniel Maier, Nadjib Mammeri, Biagio Cosenza and Ben Juurlink was announced Runner-up of Outstanding Paper Award.

The conference showcased more than 80 research papers in the areas of High Performance Computing and Simulation, with more than 200 participants from more than 30 countries.

10.07.2019: AES Paper Accepted at MASCOTS 2019

Lupe

The AES paper "Portable Cost Modeling for Auto-Vectorizers", authored by Angela Pohl, Biagio Cosenza, and Ben Juurlink, has been accepted for publication at the 27th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). The paper proposes a more accurate cost model for auto-vectorizing compilers to reduce mispredictions during their optimization stages and enable the comparison of different optimization options within the compiler.

MASCOTS will take place in Rennes, France from October 22nd to 25th. All papers will be available for open preview free of charge between September 20th and October 28th!

21.05.2019: AES paper accepted for publication at ICPP 2019.

Lupe

The paper "Predictable GPU Frequency Scaling for Energy and Performance" by AES members Kaijie Fan, Dr. Biagio Cosenza and Prof. Dr. Ben Juurlink has been accepted for publication at the 48th International Conference on Parallel Processing (ICPP). The paper proposes a method to predict the best core and memory frequency configurations on GPUs for a new OpenCL kernel without executing it.

ICPP is one of the oldest continuously running computer science conferences in parallel computing in the world. The 48th ICPP will be held in Kyoto, Japan on August 5-8, 2019.

For more information please visit: https://www.hpcs.cs.tsukuba.ac.jp/icpp2019/

20.05.2019: Four AES Papers Accepted at HPCS 2019.

Lupe

Four AES papers have been accepted at the 2019 International Conference on High Performance Computing & Simulation (HPCS 2019) which is held in Dublin, Ireland from July 15-19. They showcase the broad variety of research conducted in the AES group:

  • A Performance Analysis of Vector Length Agnostic Code by Angela Pohl, Mirko Greese, Biagio Cosenza, Ben Juurlink
  • Performance Counters based Power Modeling of Mobile GPUs using Deep Learning by Nadjib Mammeri, Markus Neu, Sohan Lal, Ben Juurlink
  • Approximating Memory-bound Applications on Mobile GPUs by Daniel Maier, Nadjib Mammeri, Biagio Cosenza, Ben Juurlink
  • Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC by Matthias Goebel, Kai Norman Clasen, Robert Drehmel and Ben Juurlink 

Under the theme of “HPC and Modeling & Simulation for the 21st Century," HPCS 2019 will focus on a wide range of the state-of-the-art as well as emerging topics pertaining to high performance and large scale computing systems at both the client and backend levels.

24.04.2019: Kaijie Fan Receives Student Grant for ACACES 2019

Lupe

Kaijie Fan has been admitted with student grant to attend the "Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2019). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.                                                                                          
                                                                                                                                                             
ACACES 2019 will take place in Fiuggi, Italy, from July 14th to July 20th, 2019.                                                                                                                                                  
For more information please visit: http://acaces.hipeac.net/2019/

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Prof. Dr. Ben Juurlink
+49.30.314-73130/73131
Raum E-N 642

Termine mit Prof. Dr. Juurlink nur nach Vereinbarung über unser Sekretariat.

Sekretariat

Sara Tennstedt
Sekr. EN 12
Raum E-N 645
Tel. +49.30.314-73130

Postanschrift

Technische Universität Berlin
Architektur eingebetteter Systeme
Sekr. EN 12
Einsteinufer 17 -6. OG
10587 Berlin