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21.05.2019: AES paper accepted for publication at ICPP 2019.

Lupe

The paper "Predictable GPU Frequency Scaling for Energy and Performance" by AES members Kaijie Fan, Dr. Biagio Cosenza and Prof. Dr. Ben Juurlink has been accepted for publication at the 48th International Conference on Parallel Processing (ICPP). The paper proposes a method to predict the best core and memory frequency configurations on GPUs for a new OpenCL kernel without executing it.

ICPP is one of the oldest continuously running computer science conferences in parallel computing in the world. The 48th ICPP will be held in Kyoto, Japan on August 5-8, 2019.

For more information please visit: https://www.hpcs.cs.tsukuba.ac.jp/icpp2019/

20.05.2019: Four AES Papers Accepted at HPCS 2019.

Lupe

Four AES papers have been accepted at the 2019 International Conference on High Performance Computing & Simulation (HPCS 2019) which is held in Dublin, Ireland from July 15-19. They showcase the broad variety of research conducted in the AES group:

  • A Performance Analysis of Vector Length Agnostic Code by Angela Pohl, Mirko Greese, Biagio Cosenza, Ben Juurlink
  • Performance Counters based Power Modeling of Mobile GPUs using Deep Learning by Nadjib Mammeri, Markus Neu, Sohan Lal, Ben Juurlink
  • Approximating Memory-bound Applications on Mobile GPUs by Daniel Maier, Nadjib Mammeri, Biagio Cosenza, Ben Juurlink
  • Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC by Matthias Goebel, Kai Norman Clasen, Robert Drehmel and Ben Juurlink 

Under the theme of “HPC and Modeling & Simulation for the 21st Century," HPCS 2019 will focus on a wide range of the state-of-the-art as well as emerging topics pertaining to high performance and large scale computing systems at both the client and backend levels.

24.04.2019: Kaijie Fan Receives Student Grant for ACACES 2019

Lupe

Kaijie Fan has been admitted with student grant to attend the "Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2019). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.                                                                                          
                                                                                                                                                             
ACACES 2019 will take place in Fiuggi, Italy, from July 14th to July 20th, 2019.                                                                                                                                                  
For more information please visit: http://acaces.hipeac.net/2019/

01.04.2019: New team member Javad Bahrami.

Lupe

AES is welcoming Javad Bahrami as a new team member. He will work in the field of Efficient Execution of Deep Neural Networks on Reconfigurable Architectures and also support the group's teaching activities. Welcome at AES, Javad!


Javad Bahrami received his B.Sc. from Iran University of Science and Technology (IUST) and his M.Sc. from University of Tehran, both in Electrical Engineering. He worked as a research assistant at University of Tehran since 2016, and during this period of time, his task was helping undergraduate students to solve their problems regarding their implementations on FPGAs by using Hardware Description Languages (HDLs). Since April 1, 2019, he joined the Embedded System Architecture (AES) group as a researcher. His research interests are FPGAs, Computer Architecture, Low-Power Circuit Design, and Parallel Programming on GPUs, to name but a few.

28.03.2018: AES@DATE 2019.

Lupe

Sohan Lal attended the 2019 edition of the international conference on Design, Automation, and Test in Europe (DATE). He presented the paper "SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs" by Sohan Lal, Jan Lucas, and Ben Juurlink.The paper proposed a novel memory access granularity aware selective approximation which intelligently trades small accuracy for higher performance.

The 2019 edition of the conference took place from March 25-29, 2019 in Florence, Italy. More information can be found at https://www.date-conference.com/

22.03.2019: Farzaneh Salehiminapour received the best student award at PARS 2019.

Lupe

AES member Farzaneh Salehiminapour received the best student award (Nachwuchspreis) at the 28th Workshop on Parallel Algorithms, Parallel Computer Structures and Parallel System Software (PARS 2019). The organizers honored Mrs. Salehiminapour for the submission and presentation of her paper “Reducing DRAM Accesses through Pseudo-Channel Mode”, co-authored by Jan Lucas, Matthias Goebel and Ben Juurlink. In this paper, the authors present and evaluate a technique to use the pseudo-channel mode feature of GDDR5X for merging memory requests and thus reducing the number of memory accesses.

The PARS workshop is organized by the special interest group on parallel algorithms, parallel computer structures and parallel system software within the German Informatics Societies (GI/ITG). Its 28th edition was held at TU Berlin in Berlin, Germany.

21+22.03.2019: the 28th edition of the PARS workshop is hosted by AES on the TU Berlin.

Lupe

On Thursday and Friday, 21rst and 22nd of March, the 28th edition of the PARS workshop is hosted by AES and taking place in the main building of TU Berlin.

PARS is a workshop organized by the special interest group on parallel algorithms, parallel computer structures and parallel system software within the German Informatics Societies (GI/ITG). The goal of the bi-annual PARS Workshop is the presentation of important research within the scope of PARS and an exchange of ideas between the participants.

The program and all other information can be found at www.aes.tu-berlin.de/menue/pars_workshop_2019/

14.03.2019, 10:30- Presentation of the H2020 project FORTIKA. Yacine Rebahi, Frauenhofer FOKUS.

Lupe
  • Title: Presentation of the H2020 project FORTIKA
  • Presenter: Yacine Rebahi, Frauenhofer FOKUS.
  • Date and time: 14.03.2019 - 10:30h
  • Room: EN 644

Dr. habil Yacine Rebahi, currently working as a senior researcher at Fraunhofer FOKUS in Berlin, will present the Horizon 2020 project FORTIKA. The projects aims at developing a cybersecurity solution for devising an intrusion prevention architecture.

20.02.2019: Four AES Papers Accepted at the PARS 2019 Workshop.

Lupe

Four papers authored by members of the AES group have been accepted for publication at the 28th edition of the PARS workshop.

18.02.2019: Ben Juurlink and Biagio Cosenza co-organizers APPMM2019 Workshop.

Lupe
Biagio Cosenza
Lupe

Prof. Juurlink and Dr. Cosenza have been invited and accepted to organize the International Workshop on Advances in Parallel Programming Models and Frameworks for the Multi-/Many-core Era (APPMM 2019) which will be held in conjunction with HPCS 2019 in Dublin, Ireland, July 15-19, 2019. The workshop tentative web page is at http://hpcs2019.cisedu.info/2-conference/workshops/workshop06-appmm. Other co-organizers are Prof. Castrillon of TU Dresden and Dr. Tagliavini of the University of Bologna.

16.02.2019: Angela Pohl PC Member of WPMVP 2019.

AES member Angela Pohl has been invited to serve as a technical program committee member for the Workshop on Programming Models for SIMD/Vector Processing (WPMVP). The workshop is co-located with PPoPP 2019 and takes place on February 16th in Washington, DC, USA. The program can be found here: https://ppopp19.sigplan.org/home/WPMVP-2019#program.

05.02.2019: AES elected to Fakultätsrat.

Lupe

AES member Angela Pohl was elected as a member of the Fakultätsrat, the faculty's central steering committee. In last weeks elections, she won one of the two seats for research assistants and will represent the group in the 2019/2020 term.

04.02.2019: AES featured in HiPEAC news.

Lupe

AES member Angela Pohl is featured in the current edition of the HiPEAC news magazine. The quaterly magazine highlights the ongoing research and academic achievements of HiPEAC members. A digital version of the magazine can be found here: https://www.hipeac.net/news/#/magazine/

24.01.2019: AES Paper accepted for publication at IPDPS 2019.

Lupe

The paper "A Bin-based Bitstream Partitioning Approach for Parallel CABAC Decoding in Next Generation Video Coding" by AES members Philipp Habermann and Prof. Dr. Ben Juurlink, as well as Chi Ching Chi and Mauricio Alvarez-Mesa from Spin Digital Video Technologies GmbH has been accepted for publication at the 33rd IEEE International Parallel and Distributed Processing Symposium (IPDPS 2019) in Rio de Janeiro, Brazil. The authors propose a modified bitstream format to address the critical entropy decoding bottleneck in high quality video decoding. Substantial speedups can be achieved while keeping the bitstream overhead at a negligible level. Especially in terms of hardware cost, the proposed method outperforms existing high-level parallelization approaches significantly.

22.01.2019: Ben Juurlink attends two events in Valencia.

Lupe

Prof. Juurlink flies to Valencia on Tuesday for two events. First, he is an Advisory Board member of the EU H2020 Projekt Tulipp and he will attend their final workshop/tutorial. Second, he will give an interview about the LPGPU2 project to Madeleine Gray of the HiPEAC Network of Excellence.


19.12.2018: Sohan Lal PC member of SummerSim'19.

Lupe

Sohan Lal has been invited to serve as a technical program committee member of the System Design Flow (SDF) track of 2019 Summer Simulation Conference (SummerSim'19) to be held from July 22-24 at Technical University of Berlin, Germany. The conference website and call for papers can be found at: http://scs.org/summersim/

10.12.18: Recap of Prof. Corporaal visiting AES.

Lupe

On Friday, September 7th, Prof. Henk Corporaal from the Embedded Systems Architectures group of  the Eindhoven University of Technology visited AES at TU Berlin.

Prof. Corporaal presented his work on accelerator architectures for Deep Learning. He covered the state-of-the-art in networks and accelerators. Prof. Corporaal also highlighted the important challenges for accelerator designs and code generation.

The talk was very well received. Besides the AES team members also members of other groups (SESE, BIGDAMA, DIMA and CV) at TU Berlin attended the event.

Afterwards, a cluster meeting was held, where deep learning accelerators and compiler technology was discussed.

9.12.2018: Insights of Prof. Lawrence Rauchwerger Research Visit.

Lupe

Prof. Dr. Lawrence Rauchwerger visited the AES group at TU Berlin from 22nd to 24th of November. On Thursday 22nd, he gave the presentation "Two Roads to Parallelism: Compilers and Libraries". Rauchwerger highlighted the importance of productivity in the context of parallel software and showed different approaches to reach it on modern parallel architectures. He presented two interesting examples: the Hybrid Analysis compiler framework, which seamlessly integrates static and run-time analysis of memory references into a single framework capable of full automatic loop level parallelization; and the SAPL library, which is a collection of generic data structures and algorithms that provides a high productivity and is the parallel programming infrastructure analogous to the C++ Standard Template Library. The event was open and many people attended his presentation from different groups, including research staff from MSD, DIMA and AES groups. After the presentation, Prof. Rauchwerger joined two round-tables organized by our group on compiler technology and computer architecture.

07.12.2018: Jan Lucas successfully completed his PhD defense.

Lupe

Dipl.-Ing. Jan Lucas successfully completed his PhD defense on Friday 7th December 2018. His thesis title was: "GPU Power Modeling and Architectural Enhancements for GPU Energy Efficiency”.
Congratulation Dr. Lucas for your success and we wish you the best in your future!

07.12.2018, 10:15h: Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?. Prof. Dr. Henk Corporaal.

Lupe
  • Title: Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?
  • Presenter: Prof. Dr. Henk Corporaal (TU Eindhoven, Netherlands)
  • Date and time: Friday December 7, 2018 - 10:15h
  • Room: EN 644

Abstract:
Deep Learning and Convolutional Neural Networks (CNNs) have revolutionized important domains like machine learning and computer vision. The huge success of deep learning accelerates research in that particular domain and thereby the complexity and diversity of state-of-the-art network models has increased significantly. This opens several challenges for CNN accelerator designers.During this presentation we will go over the state-of-the-art networks and accelerator solutions. We will present our view on compute efficiency and flexibility. We demonstrate that the well-known optimization techniques form the computing industry are key to improve efficiency. We present a holistic approach that improves efficiency by algorithmic optimizations, data reuse improvements, custom accelerators, and the less obvious but very important challenges in code generation.

Bio:
Henk Corporaal is Professor in Embedded System Architectures at the Einhoven University of Technology (TU/e) in The Netherlands. He has gained a MSc in Theoretical Physics from the University of Groningen, and a PhD in Electrical Engineering, in the area of Computer Architecture, from Delft University of Technology. 
Corporaal has co-authored over 350 journal and conference papers. Furthermore he invented a new class of VLIW architectures, the Transport Triggered Architectures, which is used in several commercial products, and by many research groups.
His research is on low power multi-processor, heterogenous processing architectures, their programmability, and the predictable design of soft- and hard real-time systems. This includes research and design of embedded system architectures, accelerators, GPUs, the exploitation of all kinds of parallelism, fault-tolerance, approximate computing, architectures for machine and deep learning, and the (semi-)automated mapping of applications to these architectures. For further details see corporaal.org.

29.11.2018: Robert Drehmel at German Academic Scholarship Foundation PhD student forum in Nuremberg.

Lupe

AES group member Robert Drehmel attends the foundation's PhD student natural sciences forum held from November 29th to December 2nd in Nuremberg.
These regularly held forums are non-public events that allow the foundation's PhD student scholarship holders to present their research projects and discuss them in small groups.
They also offer great opportunities for further, more general exchange of ideas and experiences among peers.

From the foundation's website: The Studienstiftung des deutschen Volkes – German Academic Scholarship Foundation – awards scholarships to outstanding students, irrespective of their political, ideological or
religious convictions and affiliations.

27.11.2018: LPGPU2 ends with excellent final review.

Lupe

November 27, 2018 the final review of the LPGPU2 project took place at the European Commission in Brussels. The Project Officer and the reviewers were impressed by the results of the project. Some quotes from the preliminary feedback: “… we have seen … also a set of good-quality and convincing demonstrations”, “It is also positive that companies have a clear business interest in the technologies developed in the project, …”, “Overall, the consortium demonstrated a deep know-how of power issues in modern computing architectures.”, “Scientific publications are good, …” and “… it might make sense to continue promoting the open source software.” The last quote is a clear indication that the EC and the reviewers hope that the work will be continued.

Up-right is a picture of the LPGPU2 team present at the review, but many other persons also contributed to the success of the project. From left to right: Mauricio Alvarez-Mesa (CEO Spin Digital), Nadjib Mammeri (research assistant TU Berlin), Sohan Lal (research assistant TU Berlin), Jan Lucas (previously research assistant at TU Berlin), Ben Juurlink (professor at TU Berlin and coordinator of the LPGPU2 project), Prashant Sharma (Samsung), Martyn Bliss (Samsung, media coordinator of LPGPU2), Thales Sabino (Codeplay), Ignacio Aransay Barreales (Think Silicon), Georgios Keramidas (CTO Think Silicon, technical coordinator of the project), and Haifeng Gao (Spin Digital).

26.11.2018: AES Hosts the 28th PARS Workshop.

Lupe

PARS is the special interest group on parallel algorithms, parallel computer structures and parallel system software within the German Informatics Societies (GI/ITG). The 28th edition of the bi-annual workshop is hosted by AES and will be held on March 21/22, 2019 at TU Berlin. Papers can be submitted until February 16, 2019.

Topics of interest cover all variations of parallel systems, ranging from parallel algorithms, and computing on multi-core, many-core and GPGPU architectures to future technologies like Memristors or Quantum Computing. For more information please see the call for papers on the workshop website: fg-pars.gi.de/workshops/pars-workshop-2019/

22.11.2018, 10:15h: Talk: Two Roads to Parallelism: Compilers and Libraries, Prof. Dr. Lawrence Rauchwerger (Texas A&M University, USA), Room: EN 644.

Lupe
  • Title: Two Roads to Parallelism: Compilers and Libraries
  • Presenter: Prof. Dr. Lawrence Rauchwerger (Texas A&M University, USA)
  • Date: November 22, 2018
  • Time: 10:15
  • Room: EN 644

Abstract:
Parallel computers have come of age and need parallel software to justify their usefulness. There are two major avenues to get programs to run in parallel: parallelizing compilers and parallel languages and/or libraries. In this talk we present our latest results using both approaches and draw some conclusions about their relative effectiveness and potential.
In the first part we introduce the Hybrid Analysis (HA) compiler framework that can seamlessly integrate static and run-time analysis of memory references into a single framework capable of full automatic loop level parallelization. Experimental results on 26 benchmarks show full program speedups superior to those obtained by the Intel Fortran compilers.
In the second part of this talk we present the Standard Template Adaptive Parallel Library (STAPL) based approach to parallelizing code. STAPL is a collection of generic data structures and algorithms that provides a high productivity, parallel programming infrastructure analogous to the C++ Standard Template Library (STL). In this talk, we provide an overview of the major STAPL components with particular emphasis on graph algorithms. We then present scalability results of real codes using peta scale machines such as IBM BG/Q and Cray. Finally we present some of our ideas for future work in this area.
 
Bio:
Lawrence Rauchwerger is the Eppright Professor of Computer Science and Engineering at Texas A&M University and the co-Director of the Parasol Lab. He is currently a visiting professor at ETH Zurich and will be joining the University of Illinois at Urbana-Champaign in the Fall of 2019. He received an Dipl. Engineer degree from the Polytechnic Institute Bucharest, an M.S. in Electrical Engineering from Stanford University and a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. He has held Visiting Faculty positions at the University of Illinois, Bell Labs, IBM T.J. Watson, and INRIA, Paris. Rauchwerger's approach to auto-parallelization, thread-level speculation and parallel code development has influenced industrial products at corporations such as IBM, Intel and Sun. Rauchwerger is an IEEE Fellow, an NSF CAREER award recipient and has chaired various IEEE and ACM conferences, most recently serving as Program Chair of PACT 2016 and PPoPP 2017.

09.11.2018: AES paper accepted at DATE 2019.

Lupe

The paper "SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs" by Sohan Lal, Jan Lucas, and Ben Juurlink has been accepted for publication at DATE 2019 with a long presentation. The paper proposes a novel memory access granularity aware selective approximation which intelligently trades small accuracy for a higher performance.

DATE is the top scientific event in Design, Automation, and Test of microelectronics and embedded systems for the academic and industrial research communities worldwide. The 2019 edition of the conference will take place from March 25-29 in Florence, Italy. More information can be found at https://www.date-conference.com/ 

07.11.2018: Course Computer Organisation started

View of the lecture in the audimax room.
Lupe

The course Computer Organisation has started with more than 1100 registered students. During this course students learn basic technologies and components of a computer architecture. They study number representations, computer arithmetic, performance and programming in assembly.

31.10.2018: High-performance and Embedded Computer Architecture Course on Youtube.

Lupe

We are pleased to announce that video lectures on the course "High-performance and Embedded Computer Architecture" by Prof. Juurlink are now available on AES Youtube Channel. The course covers a wide range of topics from the fundamentals of computer architecture to advanced concepts in the design of single and multi-core architectures.

Please follow the following link to access the lectures.
https://www.youtube.com/channel/UCPSsA8oxlSBjidJsSPdpjsQ/

28.10.2018: TUB Research at MICRO 51 ACM SRC.

Lupe

Sohan Lal presented his research as a poster at the 51st International Symposium on Microarchitecture (MICRO 51) in the ACM Student Research Competition.The poster was one of the six posters selected for the semi-final round. The poster presents a case for memory access granularity aware selective lossy compression for GPUs which is motivated by the observation that several state-of-the-art lossless memory compression techniques suffer due to large memory access granularity exhibited by GPUs. MICRO is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems.

This year MICRO was held in Fukuoka, Japan from 20th to 25th of October.
For more information about this year’s MICRO, please visit: https://www.microarch.org/micro51/

22.10.2018: Ben Juurlink to attend HiPEAC CSW

Lupe

Prof. Ben Juurlink will attend the HiPEAC Computing Systems Week (CSW), which will talke place from October 29 to 31 in Heraklion on the Greek island of Crete. HiPEAC is a network of excellence of researchers in the area of high-performance and embedded computer architecture and compilation. Among others this network organizes an international conference in January (the next one will take place in Valencia, Spain), computing systems weeks in Spring and Autumn, and a jobs portal.

18.10.2018: News AES team member Anastasiia Dolinina

Lupe

Anastasiia Dolinina, who is close to getting her PhD in "Radio Engineering" on the topic: "Order Reduction of Equations for Modeling of Analog Radio Engineering Devices" from "Vladimir State University", has joined the AES group. She will be collaborating with AES team members until at least 31.03.2019. She will be working on the topics: “Improvement of Macromodeling Approaches based on Model Order Reduction” and "Accelerating Machine Learning Algorithms Using Reconfigurable Architectures". Besides her work, her hobbies are listening and playing music, meeting friends and traveling.

09.10.2018: AES Paper at IISWC 2018.

Lupe

Nadjib Mammeri presented his current research conducted in the context of the LPGPU2 project at the 2018 IEEE International Symposium on Workload Characterization held in Raleigh, North Carolina, USA. He presented a paper titled "VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs".

The IISWC symposium is dedicated to the understanding and characterization of workloads that run on all types of computing systems. The symposium, sponsored by IEEE Computer Society and the Technical Committee on Computer Architecture, focuses on characterizing and understanding emerging applications in consumer, commercial and scientific computing.


For more information about this year’s program, please visit:
http://www.iiswc.org/iiswc2018/index.html

26.09.18: AES at ASIP University Day 2018

Lupe

Farzaneh Salehiminapour attended the ASIP University Day 2018 hosted by the Aachen Universuty. The event was organized by the Synopsys group. The event aimed to introduce application-specific instruction-set processors as an ideal soultion when standard processor IP cannot meet challenging application-specfic requirements.

For more information please visit https://www.synopsys.com/designware-ip/processor-solutions/asips-tools/asip-university-day-2018-europe.html

26.09.2018: Biagio Cosenza to present our autotuning research results at ScalPerf’18.

Lupe

Biagio Cosenza will attend the 16th Workshop on Scalable Approaches to High Performance and High Productivity Computing (ScalPerf'18). He will present our research on automatic tuning, in particular our latest work on optimizing stencil computations with structural learning-based methods. This research is a joint work with Juan Durillo (Leibniz Supercomputing Centre), Stefano Ermon (Stanford University) and Ben Juurlink (TU Berlin).

23.09.2018: Ben Juurlink to present LPGPU2 research results at ScalPerf’18

Lupe

Ben Juurlink will attend the 16th Workshop on Scalable Approaches to High Performance and High Productivity Computing (ScalPerf’18 ) to present LPGPU2 research results. The title of his presentation is "Power Modeling of Heterogeneous Mobile SoCs using Machine Learning”. It describes a Neural Network model that predicts the power consumption of an application running on a mobile SoC from CPU and GPU performance counters. The Neural Network model achieves a mean relative error of about 4.85%, which is twice as accurate as the state of the art. The ScalPerf workshop aims at taking an integrated look at the opportunities and constraints on the road to ever higher performance and productivity of computing systems. Distinguished researchers are invited to exchange their perspectives on different areas that can contribute to scalable computing. 

22.09.2018: AES collaboration paper published in MICPRO

Lupe

The paper "Performance Evaluation of Implicit and Explicit SIMDization" has been published in the 63rd Volume of "Microprocessors and Microsystems: Embedded Hardware Design" (MICPRO). This work is a collaborative effort between the AES group at TU Berlin and the Department of Computer Engineering at the University of Guilan, Iran.

In this work, the authors analyze the vectorization capabilities of general purpose compilers and present an approach based code modification technique that targets implementations with loop collapsing, loop unrolling, software pipelining, or loop exchange.

MICPRO is a journal covering all design and architectural aspects related to embedded systems hardware.

21.09.2018: AES presents at IEEE CLUSTER 2018 and ARM Research Summit.

Lupe

AES member Angela Pohl presented her work on "Cost Modelling for Vectorization on ARM" at two events in the UK: the REV-A workshop, co-located with IEEE CLUSTER 2018 in Belfast, and the ARM Research Summit in Cambridge.

In her research, Angela analyzes the accuracy of current performance predictions within compilers' auto-vectorizers and shows potential for increased vectorization rates due to exact instruction cost models. You can re-watch her presentation from the vectorization session at the ARM Research Summit  here  .

The IEEE Cluster Conference serves as a major international forum for presenting and sharing recent accomplishments and technological developments in the field of cluster computing as well as the use of cluster systems for scientific and commercial applications.

At the Arm Research Summit, academics, researchers and industry experts meet to discuss the latest developments in computing research and practical computing challenges. 

20.09.2018: Ben Juurlink PC member of IPDPS and ARCS

Lupe

Prof. Ben Juurlink, chairman of the AES group, has been invited to join the program committees of the International Parallel and Distributing Processing Symposium (IPDPS 2019) to be held in Rio de Janeiro, Brazil and the International Conference on Architecture of Computing Systems (ARCS 2019) to be held in Braunschweig, Germany.

12.09.2018: LPGPU2 tool-suite helps to extend mobile battery life without sacrificing performance or quality.

http://lpgpu.org/
Lupe

European Union-funded researchers have today released a tool suite which enables developers to deliver longer battery life in mobile devices, while ensuring high quality and performance.

The LPGPU2 tool-suite helps programmers develop power-efficient code for GPUs by identifyingc bottlenecks relating to performance (for example in terms of frames-per-second) and power (for example in terms of energy per instruction).

“The LPGPU2 tool will have a major impact on applications where ultra-low power or high performance graphics are priorities," explains LPGPU2 Coordinator Ben Juurlink, professor of embedded systems architectures at TU Berlin. “Thanks to the breakthrough techniques developed by LPGPU2's academic and industry experts, innovative applications in a wide range of domains, including healthcare, fitness, security, infotainment and autonomous vehicles, are now possible."

By providing an end-to-end solution that starts at the application and reaches all the way to the hardware, the tool-suite provides insights and visibility not possible in other tools. This coupled with the Feedback Engine – a unique part of the tool suite that makes optimization simple by providing insightful guidance on how to improve performance and power consumption – provides an unbeatable combination.

The LPGPU2 tool suite has benefited from the expertise of a range of academic and industrial partners. TU Berlin developed the power measurement tool, while Samsung designed and implemented the data collection frameworks, the feedback engine (that functions as a virtual optimization expert) and also tested the tool suite on real mobile devices. Greek company Think Silicon validated it on their four-core NEMA GPU system. Meanwhile, Scottish software specialists Codeplay extended AMD’s CodeXL tool, allowing programmers to profile their SYCL applications, and Berlin-based video experts Spin Digital produced a high-performance, multi-API video player, which delivers performance gains of up to 25% as well as energy usage reduction of up to 25%.

Download the tool suite now from the GitHub repository:
https://github.com/codeplaysoftware/LPGPU2-CodeXL


About LPGPU2
LPGPU2 helps developers create software for low-power GPUs by providing a complete performance and power analysis process for the programmer. Building on LPGPU1, the project addresses all aspects of performance analysis, from hardware power and performance counters, to a framework that processes and visualizes information from these counters, to use-case applications driving the entire design. Led by TU Berlin, LPGPU2's unique consortium brings together world-class academic researchers with leading European technology companies. The team combines academic experience in research, theory, and analysis with industry expertise in terms of applications in practice, reaching production maturity and commercialization of the technology.


LPGPU2 has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement no. 688759.


Further information:
Professor Ben Juurlink, TU Berlin
Email: coordinator@lpgpu.org
Web: www.lpgpu.org
Tel: +49.30.314-73130

27.08.2018: AES-paper accepted at IISWC 2018.

Lupe

The paper "VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs" by Nadjib Mammeri and Ben Juurlink has been accepted at IISWC 2018. The paper proposes VComputeBench, a set of benchmarks that help developers understand the differences in performance and portability of Vulkan and evaluates its suitability as an emerging cross-platform GPGPU framework by conducting a thorough analysis of its performance compared to CUDA and OpenCL on mobile as well as on desktop platforms.

The IEEE International Symposium on Workload Characterization is a well-established symposium for state-of-the-art research dedicated to the understanding and characterization of workloads that run on all types of computing systems. The 2018 edition of this conference will take place from September 30-October 2, 2018 in Raleigh, North Carolina, USA .

More information can be found at IISWC-2018.

01.08.18: AES Presentation at Euro-Par 2018.

The paper "OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations" written by Biagio Cosenza, Nikita Popov and Ben Juurlink in collaboration with researchers from the University of Sheffield and the University of Salerno, has been accepted at the International Conference on Parallel and Distributed Computing (Euro-Par) 2018. The artifact of the paper has also received a positive artifact evaluation. Dr. Cosenza will present this work at the Euro-Par conference in August 30 at the Luigi Einaudi University Campus, Turin, Italy.

Paper preprint: http://biagiocosenza.com/papers/CosenzaEUROPAR18.pdf
Project source code: https://github.com/OpenABL/OpenABL
Evaluated artifact: https://figshare.com/s/3ef16d36a5896000b85a

Paper info: OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations Biagio Cosenza, Nikita Popov, Ben Juurlink, Paul Richmond, Mozhgan Kabiri Chimeh, Carmine Spagnuolo, Gennaro Cordasco, Vittorio Scarano International European Conference on Parallel and Distributed Computing (Euro-Par), 2018 Acceptance rate: 29%

More information can be found at https://europar2018.org

Dr. Cosenza will also be Session Chair for the session 4A on Applications.
Euro-Par Program: https://europar2018.org/program

17.07.18: Offert for master projekt.

Lupe

In a joint project between the TU Berlin research group “Embedded Systems Architecture” and the PTB research group “Quantitative MRI” we are looking for an MSc student to optimize MR image reconstruction algorithms for medical imaging applications to ensure we can translate novel image reconstruction techniques efficiently to the clinics and help improve patient care.
Your background:

  • student of computer studies, electrical engineering or in a comparable area of engineering/natural sciences
  • experience with CUDA
  • ability and dedication to work in an interdisciplinary biomedical research environment

Please see attached dokument for Detaills.

31.05.2018: Best Presentation Award at SCOPES '18.

Lupe

AES member Angela Pohl received the Best Presentation Award at the 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES `18). She presented the full paper “Control Flow Vectorization for ARM NEON”, which was co-authored by Nicolás Morini, Biagio Cosenza, and Ben Juurlink. In this work, the authors discuss the capabilities of compilers’ auto-vectorization passes and present strategies to overcome the missing masked instructions on ARM NEON platforms, which are critical to vectorize loops with control flow. The work was selected for the award by attendee vote.

The 21st edition of SCOPES was held in St. Goar, Germany, and showcased more than 20 presentations from the field of embedded systems. More information about this ACM sponsored event can be found here: https://www.scopesconf.org/scopes-18/ .

24.05.2018: AES at RAW@IPDPS 2018.

Lupe

Matthias Göbel attended the 25th Reconfigurable Architectures Workshop (RAW) at the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018). He presented the paper “An Application-Specific Memory Management Unit for FPGA-SoCs” by Matthias Göbel, Ilja Behnke, Ahmed Elhossini and Ben Juurlink. During the workshop, it was announced that the paper had been one out of three candidates for the Best Short Paper Award.

The 25th Reconfigurable Architectures Workshop (RAW 2018) has been held in Vancouver, British Columbia, Canada in May 2018. RAW 2018 is associated with the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing.

More information can be found at http://www.ipdps.org/ipdps2018/.

15.05.2018: Biao Wang successfully completed his PhD defense.

Lupe

M.Sc. Biao Wang successfully completed his PhD defense on Tuesday 15th May 2018. His thesis title was: "High-performance Video Decoding using Graphics Processing Units”.
Congratulation Dr. Wang for your success and we wish you the best in your future! 

18.04.18: Sohan Lal Selected With Student Grant to Attend ACACES 2018.

Lupe

Sohan Lal has been selected with student grant to attend the "Fourteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2018). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.

ACACES 2018 will take place in Fiuggi, Italy, from July 8th to July 14th, 2018.
For more information please visit: http://acaces.hipeac.net/2018/index.php

March 19-23, 2018: AES Presentation at DATE 2018.

Lupe

Jan Lucas will present the paper "Optimal DC/AC Data Bus Inversion Coding" at DATE 2018 in Dresden. The paper is part of the "Emerging architectures and technologies for ultra low power and efficient embedded systems" Session on Thursday and presents a novel encoding technique that reduces the power consumption of the memory interface by up to 6%. DATE (Design, Automation and Test in Europe) is the European event for Electronic System Design and Test. More information can be found at https://www.date-conference.com/.

07.03.2018: AES-paper accepted at RAW 2018.

Lupe

The paper “An Application-Specific Memory Management Unit for FPGA-SoCs” by Matthias Göbel, Ilja Behnke and Ben Juurlink has been accepted at the 25th Reconfigurable Architectures Workshop (RAW) at IPDPS 2018. In the paper, we present an MMU that can be used to enable memory virtualization in the FPGA part of an FPGA-SoC. Enabling memory virtualization reduces the overhead of implementing HW/SW-Codesign approaches significantly.

The 25th Reconfigurable Architectures Workshop (RAW 2018) will be held in Vancouver, British Columbia, Canada in May 2018. RAW 2018 is associated with the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing.

February 24 - 28th, 2018: AES presentation at CGO 2018.

Biagio Cosenza and Daniel Maier are attending the co-located conferences HPCA/CGO/PPoPP/CC, that are held in Vienna, Austria between February 24th and 28th. Daniel Maier is presenting their work on "Local Memory-Aware Kernel Perforation", that has been accepted as a paper at CGO. The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. Principles and Practice of Parallel Programming (PPoPP) is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience. 

January 22-24, 2018: AES presentations at HiPEAC18.

Lupe

Jan Lucas, Matthias Göbel and Nadjib Mammeri visited the 13th HiPEAC Conference in Manchester from Jan 22nd to Jan 24th. They presented their work both by giving invited talks at the PEGPUM workshop, which was co-organized by AES, as well as by taking part in the poster sessions. The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems.

More information can be found at https://www.hipeac.net/2018/manchester/.

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