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Welcome at AES


The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.


12.09.2018: LPGPU2 tool-suite helps to extend mobile battery life without sacrificing performance or quality.


European Union-funded researchers have today released a tool suite which enables developers to deliver longer battery life in mobile devices, while ensuring high quality and performance.

The LPGPU2 tool-suite helps programmers develop power-efficient code for GPUs by identifyingc bottlenecks relating to performance (for example in terms of frames-per-second) and power (for example in terms of energy per instruction).

“The LPGPU2 tool will have a major impact on applications where ultra-low power or high performance graphics are priorities," explains LPGPU2 Coordinator Ben Juurlink, professor of embedded systems architectures at TU Berlin. “Thanks to the breakthrough techniques developed by LPGPU2's academic and industry experts, innovative applications in a wide range of domains, including healthcare, fitness, security, infotainment and autonomous vehicles, are now possible."

By providing an end-to-end solution that starts at the application and reaches all the way to the hardware, the tool-suite provides insights and visibility not possible in other tools. This coupled with the Feedback Engine – a unique part of the tool suite that makes optimization simple by providing insightful guidance on how to improve performance and power consumption – provides an unbeatable combination.

The LPGPU2 tool suite has benefited from the expertise of a range of academic and industrial partners. TU Berlin developed the power measurement tool, while Samsung designed and implemented the data collection frameworks, the feedback engine (that functions as a virtual optimization expert) and also tested the tool suite on real mobile devices. Greek company Think Silicon validated it on their four-core NEMA GPU system. Meanwhile, Scottish software specialists Codeplay extended AMD’s CodeXL tool, allowing programmers to profile their SYCL applications, and Berlin-based video experts Spin Digital produced a high-performance, multi-API video player, which delivers performance gains of up to 25% as well as energy usage reduction of up to 25%.

Download the tool suite now from the GitHub repository:


27.08.2018: AES-paper accepted at IISWC 2018.


The paper "VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs" by Nadjib Mammeri and Ben Juurlink has been accepted at IISWC 2018. The paper proposes VComputeBench, a set of benchmarks that help developers understand the differences in performance and portability of Vulkan and evaluates its suitability as an emerging cross-platform GPGPU framework by conducting a thorough analysis of its performance compared to CUDA and OpenCL on mobile as well as on desktop platforms.

The IEEE International Symposium on Workload Characterization is a well-established symposium for state-of-the-art research dedicated to the understanding and characterization of workloads that run on all types of computing systems. The 2018 edition of this conference will take place from September 30-October 2, 2018 in Raleigh, North Carolina, USA .

More information can be found at IISWC-2018.

01.08.18: AES Presentation at Euro-Par 2018.

The paper "OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations" written by Biagio Cosenza, Nikita Popov and Ben Juurlink in collaboration with researchers from the University of Sheffield and the University of Salerno, has been accepted at the International Conference on Parallel and Distributed Computing (Euro-Par) 2018. The artifact of the paper has also received a positive artifact evaluation. Dr. Cosenza will present this work at the Euro-Par conference in August 30 at the Luigi Einaudi University Campus, Turin, Italy.

Paper preprint: http://biagiocosenza.com/papers/CosenzaEUROPAR18.pdf
Project source code: https://github.com/OpenABL/OpenABL
Evaluated artifact: https://figshare.com/s/3ef16d36a5896000b85a

Paper info: OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations Biagio Cosenza, Nikita Popov, Ben Juurlink, Paul Richmond, Mozhgan Kabiri Chimeh, Carmine Spagnuolo, Gennaro Cordasco, Vittorio Scarano International European Conference on Parallel and Distributed Computing (Euro-Par), 2018 Acceptance rate: 29%

More information can be found at https://europar2018.org

Dr. Cosenza will also be Session Chair for the session 4A on Applications.
Euro-Par Program: https://europar2018.org/program

More news can be found here.

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Group Chair

Prof. Dr. Ben Juurlink
Room E-N 642

Secretary's office

Sara Tennstedt
sec. EN 12
Room E-N 645

Drop-In Hours:
Tue 10-12, Thu 12-14
or by appointment

Postal address

Technische Universität Berlin
Architektur eingebetteter Systeme
sec. EN 12
Einsteinufer 17 -6. OG
10587 Berlin