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Welcome at AES


The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

Above is a picture of the AES Team.  From left to right: Anastasiia Dolinina, Farzaneh Salehiminapour, Robert Drehmel, Biagio Cosenza, Sohan Lal, Adela Westedt, Daniel Maier, Ben Juurlink, Matthias Göbel, Kaijie Fan, Nadjib Mammeri, Sara Tennstedt, Angela Pohl and Philipp Habermann.


24.04.2009: Kaijie Fan Receives Student Grant for ACACES 2019.


Kaijie Fan has been admitted with student grant to attend the "Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2019). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.                                                                                          
ACACES 2019 will take place in Fiuggi, Italy, from July 14th to July 20th, 2019.                                                                                                                                                  
For more information please visit: http://acaces.hipeac.net/2019/

01.04.2019: New team member Javad Bahrami.


AES is welcoming Javad Bahrami as a new team member. He will work in the field of Efficient Execution of Deep Neural Networks on Reconfigurable Architectures and also support the group's teaching activities. Welcome at AES, Javad!

Javad Bahrami received his B.Sc. from Iran University of Science and Technology (IUST) and his M.Sc. from University of Tehran, both in Electrical Engineering. He worked as a research assistant at University of Tehran since 2016, and during this period of time, his task was helping undergraduate students to solve their problems regarding their implementations on FPGAs by using Hardware Description Languages (HDLs). Since April 1, 2019, he joined the Embedded System Architecture (AES) group as a researcher. His research interests are FPGAs, Computer Architecture, Low-Power Circuit Design, and Parallel Programming on GPUs, to name but a few.

28.03.2018: AES@DATE 2019.


Sohan Lal attended the 2019 edition of the international conference on Design, Automation, and Test in Europe (DATE). He presented the paper "SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs" by Sohan Lal, Jan Lucas, and Ben Juurlink.The paper proposed a novel memory access granularity aware selective approximation which intelligently trades small accuracy for higher performance.

The 2019 edition of the conference took place from March 25-29, 2019 in Florence, Italy. More information can be found at https://www.date-conference.com/

More news can be found here.

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Auxiliary Functions

Group Chair

Prof. Dr. Ben Juurlink
Room E-N 642

Consultation with Prof. Dr. Juurlink only by appointment via our secretary.

Secretary's office

Sara Tennstedt
sec. EN 12
Room E-N 645

Drop-In Hours:
Tue 10-12, Thu 12-14
or by appointment

Postal address

Technische Universität Berlin
Architektur eingebetteter Systeme
sec. EN 12
Einsteinufer 17 -6. OG
10587 Berlin