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Welcome at AES


The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

Above is a picture of the AES Team.  From left to right: Anastasiia Dolinina, Farzaneh Salehiminapour, Robert Drehmel, Biagio Cosenza, Sohan Lal, Adela Westedt, Daniel Maier, Ben Juurlink, Matthias Göbel, Kaijie Fan, Nadjib Mammeri, Sara Tennstedt, Angela Pohl and Philipp Habermann.


05.02.2019: AES elected to Fakultätsrat.


AES member Angela Pohl was elected as a member of the Fakultätsrat, the faculty's central steering committee. In last weeks elections, she won one of the two seats for research assistants and will represent the group in the 2019/2020 term.

04.02.2019: AES featured in HiPEAC news.


AES member Angela Pohl is featured in the current edition of the HiPEAC news magazine. The quaterly magazine highlights the ongoing research and academic achievements of HiPEAC members. A digital version of the magazine can be found here: https://www.hipeac.net/news/#/magazine/

24.01.2019: AES Paper accepted for publication at IPDPS 2019.


The paper "A Bin-based Bitstream Partitioning Approach for Parallel CABAC Decoding in Next Generation Video Coding" by AES members Philipp Habermann and Prof. Dr. Ben Juurlink, as well as Chi Ching Chi and Mauricio Alvarez-Mesa from Spin Digital Video Technologies GmbH has been accepted for publication at the 33rd IEEE International Parallel and Distributed Processing Symposium (IPDPS 2019) in Rio de Janeiro, Brazil. The authors propose a modified bitstream format to address the critical entropy decoding bottleneck in high quality video decoding. Substantial speedups can be achieved while keeping the bitstream overhead at a negligible level. Especially in terms of hardware cost, the proposed method outperforms existing high-level parallelization approaches significantly.

More news can be found here.

Zusatzinformationen / Extras

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Auxiliary Functions

Group Chair

Prof. Dr. Ben Juurlink
Room E-N 642

Consultation with Prof. Dr. Juurlink only by appointment via our secretary.

Secretary's office

Sara Tennstedt
sec. EN 12
Room E-N 645

Drop-In Hours:
Tue 10-12, Thu 12-14
or by appointment

Postal address

Technische Universität Berlin
Architektur eingebetteter Systeme
sec. EN 12
Einsteinufer 17 -6. OG
10587 Berlin