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Inhalt des Dokuments

Welcome at AES


The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.


07.12.2018, 10:15h: Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?. Prof. Dr. Henk Corporaal.

  • Title: Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?
  • Presenter: Prof. Dr. Henk Corporaal (TU Eindhoven, Netherlands)
  • Date and time: Thursday December 7, 2018 - 10:15h
  • Room: EN 644

Deep Learning and Convolutional Neural Networks (CNNs) have revolutionized important domains like machine learning and computer vision. The huge success of deep learning accelerates research in that particular domain and thereby the complexity and diversity of state-of-the-art network models has increased significantly. This opens several challenges for CNN accelerator designers.During this presentation we will go over the state-of-the-art networks and accelerator solutions. We will present our view on compute efficiency and flexibility. We demonstrate that the well-known optimization techniques form the computing industry are key to improve efficiency. We present a holistic approach that improves efficiency by algorithmic optimizations, data reuse improvements, custom accelerators, and the less obvious but very important challenges in code generation.

22.11.2018, 10:15h: Talk: Two Roads to Parallelism: Compilers and Libraries, Prof. Dr. Lawrence Rauchwerger (Texas A&M University, USA), Room: EN 644.

  • Title: Two Roads to Parallelism: Compilers and Libraries
  • Presenter: Prof. Dr. Lawrence Rauchwerger (Texas A&M University, USA)
  • Date: November 22, 2018
  • Time: 10:15
  • Room: EN 644

Parallel computers have come of age and need parallel software to justify their usefulness. There are two major avenues to get  programs to run in parallel: parallelizing compilers and parallel languages and/or libraries. In this talk we present our latest results  using both approaches and draw some conclusions about their relative effectiveness and potential.
In the first part we introduce the Hybrid Analysis (HA) compiler framework that can seamlessly integrate static and run-time analysis of memory references into a single framework capable of full automatic loop level parallelization. Experimental results on 26 benchmarks show full program speedups superior to those obtained by the Intel Fortran compilers.
In the second part of this talk we present the Standard Template Adaptive Parallel Library (STAPL) based approach to parallelizing code. STAPL is a collection of generic data structures and algorithms that provides a high productivity, parallel programming infrastructure analogous to the C++ Standard Template Library (STL). In this talk, we provide an overview of the major STAPL components with particular emphasis on graph algorithms. We then present scalability results of real codes using peta scale machines such as IBM BG/Q and Cray. Finally we present some of our ideas for future work in this area.

09.11.2018: AES paper accepted at DATE 2019.


The paper "SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs" by Sohan Lal, Jan Lucas, and Ben Juurlink has been accepted for publication at DATE 2019 with a long presentation. The paper proposes a novel memory access granularity aware selective approximation which intelligently trades small accuracy for a higher performance.

DATE is the top scientific event in Design, Automation, and Test of microelectronics and embedded systems for the academic and industrial research communities worldwide. The 2019 edition of the conference will take place from March 25-29 in Florence, Italy. More information can be found at https://www.date-conference.com/ 

07.11.2018: Vorlesung Rechnerorganisation hat begonnen.


Die Vorlesung Rechnerorganisation hat mit mehr als 1100 Anmeldungen begonnen! Im Rahmen dieser Veranstaltung lernen Studierende aus den Studiengängen Informatik, Technische Informatik, Medieninformatik und des Wirtschaftsingenieurwesens die grundlegende Technologien und Komponenten einer Rechnerarchitektur kennen. Sie befassen sich u.a. mit der Zahlendarstellung und Rechnerarithmetik, Leistung  und der Programmierung in Maschinensprache und Assembler.

More news can be found here.

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Auxiliary Functions

Group Chair

Prof. Dr. Ben Juurlink
Room E-N 642

Secretary's office

Sara Tennstedt
sec. EN 12
Room E-N 645

Drop-In Hours:
Tue 10-12, Thu 12-14
or by appointment

Postal address

Technische Universität Berlin
Architektur eingebetteter Systeme
sec. EN 12
Einsteinufer 17 -6. OG
10587 Berlin