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Inhalt des Dokuments

Welcome at AES

Lupe

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

News

09.10.2018: AES Paper at IISWC 2018.

Lupe

Nadjib Mammeri presented his current research conducted in the context of the LPGPU2 project at the 2018 IEEE International Symposium on Workload Characterization held in Raleigh, North Carolina, USA. He presented a paper titled "VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs".

The IISWC symposium is dedicated to the understanding and characterization of workloads that run on all types of computing systems. The symposium, sponsored by IEEE Computer Society and the Technical Committee on Computer Architecture, focuses on characterizing and understanding emerging applications in consumer, commercial and scientific computing.


For more information about this year’s program, please visit:
http://www.iiswc.org/iiswc2018/index.html

26.09.18: AES at ASIP University Day 2018

Lupe

Farzaneh Salehiminapour attended the ASIP University Day 2018 hosted by the Aachen Universuty. The event was organized by the Synopsys group. The event aimed to introduce application-specific instruction-set processors as an ideal soultion when standard processor IP cannot meet challenging application-specfic requirements.

For more information please visit https://www.synopsys.com/designware-ip/processor-solutions/asips-tools/asip-university-day-2018-europe.html

26.09.2018: Biagio Cosenza to present our autotuning research results at ScalPerf’18.

Lupe

Biagio Cosenza will attend the 16th Workshop on Scalable Approaches to High Performance and High Productivity Computing (ScalPerf'18). He will present our research on automatic tuning, in particular our latest work on optimizing stencil computations with structural learning-based methods. This research is a joint work with Juan Durillo (Leibniz Supercomputing Centre), Stefano Ermon (Stanford University) and Ben Juurlink (TU Berlin).

23.09.2018: Ben Juurlink to present LPGPU2 research results at ScalPerf’18

Lupe

Ben Juurlink will attend the 16th Workshop on Scalable Approaches to High Performance and High Productivity Computing (ScalPerf’18 ) to present LPGPU2 research results. The title of his presentation is "Power Modeling of Heterogeneous Mobile SoCs using Machine Learning”. It describes a Neural Network model that predicts the power consumption of an application running on a mobile SoC from CPU and GPU performance counters. The Neural Network model achieves a mean relative error of about 4.85%, which is twice as accurate as the state of the art. The ScalPerf workshop aims at taking an integrated look at the opportunities and constraints on the road to ever higher performance and productivity of computing systems. Distinguished researchers are invited to exchange their perspectives on different areas that can contribute to scalable computing. 

More news can be found here.

Zusatzinformationen / Extras

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Auxiliary Functions

The secretary’s office will be closed from October 24-30, 2018.

Group Chair

Prof. Dr. Ben Juurlink
+49.30.314-73130/73131
Room E-N 642

Secretary's office

Sara Tennstedt
sec. EN 12
Room E-N 645
+49.30.314-73130

Drop-In Hours:
Tue 10-12, Thu 12-14
or by appointment

Postal address

Technische Universität Berlin
Architektur eingebetteter Systeme
sec. EN 12
Einsteinufer 17 -6. OG
10587 Berlin