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A Generic Implementation of a Quantified Predictor Applied to a DRAM Power-Saving Policy
Zitatschlüssel Thomas2014
Autor Gervin Thomas
Buchtitel PhD Thesis,
Jahr 2014
Monat August
Schule Technische Universität Berlin
Zusammenfassung Predictors are used in many subfields of computer architecture to enhance performance. Accurate estimations of future system behavior allow to develop policies to improve system performance or reduce power consumption. These policies become more efficient if predictors are implemented in hardware and are able to provide quantified forecasts, i.e. providing more than binary forecasts. One of the most important goals of any computer system, from servers to battery-driven hand-held devices, is the reduction of power and energy consumption. To achieve this, the energy consumption of all system components must be reduced. This is especially important for off-chip DRAM, which consumes a significant amount of energy even when it is idle. Hence, DRAMs support different power-saving modes, such as self-refresh and power-down. However, employing these power-saving modes each time the DRAM is idle, impacts the performance due to their power-up latencies. The self-refresh mode offers large power saving potential, but incurs a long power-up latency. The power-down mode, on the other hand, has a lower power-up latency but provides less power savings. Using the most efficient mode depends on the length of the idle period, which is normally unknown. This thesis presents and evaluates a history-based predictor which produces quantified forecasts. A software version and a hardware implementation of the prediction algorithm are implemented and analyzed. A complete design space analysis of the predictor is presented to determine parameter sets achieving an accuracy rate over 96%. Moreover, a generic and fully synthesizeable design is presented in VHDL and implemented on an FPGA. A complete scalability analysis of the hardware predictor shows that the design has a low device utilization and can be clocked by over 210 MHz. Using the impact of the previous analyses, a predictor-based power-saving policy is presented for the reduction of memory power consumption. This power-saving policy combines the two power-saving modes, self-refresh and power-down, in order to achieve significant power reductions with marginal performance penalties. The history-based predictor is then used to forecast the duration of idle periods and apply either self-refresh, power-down, or a combination of both power-saving modes. The policy is evaluated using applications from the multimedia domain. The experimental results exhibit that it reduces the total DRAM energy consumption between 43.4% and 65.8% at a negligible performance penalty between 0.34% and 2.18%.
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