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TU Berlin

Inhalt des Dokuments

Publikationen

Scalable Parallel Programming Applied to H.264/AVC Decoding

Ben Juurlink and Mauricio Alvarez-Mesa and Chi Ching Chi and Arnaldo Azevedo and Cor Meenderinck and Alex Ramirez

||Springer. 2012

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A Trace-based Workflow for Evaluating Application-specific Memory Bandwidth for FPGA-SoCs

Matthias Göbel and Ahmed Elhossini and Ben Juurlink

Proceedings of the 12th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2016) 2016

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Topology-aware Equipartitioning with Coscheduling on Multicore Systems

Jan H. Schönherr and Ben Juurlink and Jan Richling

6th International Workshop on Multi-/Many-core Computing Systems. 2013

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On Latency in GPU Throughput Microarchitectures

Michael Andersch and Jan Lucas and Mauricio Alvarez-Mesa and Ben Juurlink

Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS), 169-170. 2015

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Local Memory-Aware Kernel Perforation

Daniel Maier and Biagio Cosenza and Ben Juurlink

Proceedings of the 2018 International Symposium on Code Generation and Optimization. ACM. 2018

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DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads

Jan Lucas and Sohan Lal and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink

Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13) 2013

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A Generic Implementation of a Quantified Predictor for FPGAs

Gervin Thomas and Ahmed Elhossini and Ben Juurlink

GLSVLSI '14: Proceedings of the 24th ACM International Conference on Great Lakes Symposium on VLSI. ACM. 2014

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Exploring GPGPUs Workload Characteristics and Power Consumption

Sohan Lal and Jan Lucas and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink

Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13) 2013

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Entwurf eines generischen, applikationsspezifischen,transportgesteuerten Prozessor-Modells in VHDL und Validierung auf einem FPGA

Stefan Hauser

Informatiktage 2010, Fachwissenschaftlicher Informatik-Kongress. Gesellschaft für Informatik, 169 – 172. 2010

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Improving the Parallelization Efficiency of HEVC Decoding

Chi Ching Chi and Mauricio Alvarez Mesa and Ben Juurlink and V. George and T. Schierl

Proceedings of the 2012 International Conference on Image Processing (ICIP) 2013

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Analyzing GPGPU Pipeline Latency

Michael Andersch and Jan Lucas and Mauricio Alvarez-Mesa and Ben Juurlink

Proc. 10th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 14) 2014

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ALUPower: Data Dependent Power Consumption in GPUs

Jan Lucas and Ben Juurlink

Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2016 IEEE 23rd International Symposium on 2016

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A data access prediction unit for multimedia applications

Tareq Alawneh and Ahmed Elhossini

2016 28th International Conference on Microelectronics (ICM), 125-128. 2016

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Efficient HEVC decoder for heterogeneous CPU with GPU systems

Biao Wang and Diego F. de Souza and Mauricio Alvarez-Mesa and Chi Ching Chi and Ben Juurlink and Aleksandar Ilic and Nuno Roma and Leonel Sousa

2016 IEEE 18th International Workshop on Multimedia Signal Processing (MMSP), 1-6. 2016

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Transport Triggered Interconnection Network for a Scalable Application-Specific Processor

Stefan Hauser and Nico Moser and Carsten Gremzow and Ben Juurlink

ACACES 2010 - Poster Abstracts. High Performance and Embedded Architecture and Compilation, 155–158. 2010

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Ältere Publikationen

Ältere Publikationen von Prof. Juurlink finden sich hier.

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