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TU Berlin

Inhalt des Dokuments

Publikationen

G

Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC

Matthias Göbel and Kai Norman Clasen and Robert Drehmel and Ben Juurlink

Proceedings of the 17th International Conference on High Performance Computing & Simulation (HPCS 2019). Nominee for Outstanding Paper Award. 2019

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An Application-Specific Memory Management Unit for FPGA-SoCs

Matthias Göbel and Ilja Behnke and Ahmed Elhossini and Ben Juurlink

Proceedings of the 25th Reconfigurable Architectures Workshop (RAW 2018) at the 32nd IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018). Nominee for Best Short Paper Award. 2018

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A Trace-based Workflow for Evaluating Application-specific Memory Bandwidth for FPGA-SoCs

Matthias Göbel and Ahmed Elhossini and Ben Juurlink

Proceedings of the 12th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2016) 2016

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A Quantitative Analysis of the Memory Architecture of FPGA-SoCs

Matthias Göbel and Ahmed Elhossini and Chi Ching Chi and Mauricio Alvarez-Mesa and Ben Juurlink

Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC 2017). Best Paper Award winner. 2017

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High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis

Matthias Göbel and Chi Ching Chi and Mauricio Alvarez-Mesa and Ben Juurlink

Proceedings of the 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2015). HiPEAC Paper Award. 2015

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H

Application-specific Cache and Prefetching for HEVC CABAC Decoding

Philipp Habermann and Chi Ching Chi and Mauricio Alvarez-Mesa and Ben Juurlink

IEEE Multimedia, Volume 24, Issue 1, Jan.-Mar. 2017, 72-85. 2017

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Design and Implementation of a High-Throughput CABAC Hardware Accelerator for the HEVC Decoder

Philipp Habermann

Lecture Notes in Informatics - Seminars, Informatiktage 2014, 213-216. 2014

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Improved Wavefront Parallel Processing for HEVC Decoding

Philipp Habermann and Chi Ching Chi and Mauricio Alvarez-Mesa and Ben Juurlink

Proceedings of the 13th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2017), 253-256. 2017

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Syntax Element Partitioning for high-throughput HEVC CABAC Decoding

Philipp Habermann and Chi Ching Chi and Mauricio Alvarez-Mesa and Ben Juurlink

Proceedings of the 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2017), 1308-1312. 2017

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Memory-aware Weight Pruning for Deep Neural Networks.

Thomas Hartenstein and Daniel Maier and Biagio Cosenza and Ben Juurlink

PARS-Mitteilungen, (to appear) 2019,

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Entwurf eines generischen, applikationsspezifischen,transportgesteuerten Prozessor-Modells in VHDL und Validierung auf einem FPGA

Stefan Hauser

Informatiktage 2010, Fachwissenschaftlicher Informatik-Kongress. Gesellschaft für Informatik, 169 – 172. 2010

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Transport Triggered Interconnection Network for a Scalable Application-Specific Processor

Stefan Hauser and Nico Moser and Carsten Gremzow and Ben Juurlink

ACACES 2010 - Poster Abstracts. High Performance and Embedded Architecture and Compilation, 155–158. 2010

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Spectral turning bands for efficient Gaussian random fields generation on GPUs and accelerators

Lars Hunger and Biagio Cosenza and Stefan Kimeswenger and Thomas Fahringer

Concurrency and Computation: Practice and Experience, n/a–n/a. 2015

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J

Enabling GPU software developers to optimize their applications - The LPGPU\(^mbox2\) approach

Ben H. H. Juurlink and Jan Lucas and Nadjib Mammeri and Georgios Keramidas and Katerina Pontzolkova and Ignacio Aransay and Chrysa Kokkala and Martyn Bliss and Andrew Richards

2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017, Dresden, Germany, September 27-29, 2017. IEEE, 1–6. 2017

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Ältere Publikationen

Ältere Publikationen von Prof. Juurlink finden sich hier.

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