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Free configurable VLIW/TTA Hybrid Architecture

Description

Lupe

Very Long Instruction Word (VLIW) and so-called Transport Triggered Architectures (TTA) are potentially simpler and hence more power-efficient than superscalar architectures since they do not need hardware to detect instruction-level parallelism. We have developed an FPGA-prototype of a hybrid VLIW/TTA architecture named SynZEN. It consists of a customizable set of functional units (FUs) with associated register files and a customizable interconnection network between the FUs. SynZEN is less complex than a VLIW architecture because the register file is fully distributed while in a VLIW several or all FUs share a register file. It is less complex than a TTA architecture because data out of a local register files can be used instead of a transportation step throw the network . The goal of this project is to extend the SynZEN architecture with several features such as caches and to develop compiler support for it. Furthermore, we intend to investigate how the SynZEN architecture can be deployed as an ILP accelerator in heterogeneous multicores.

People involved

Publications

SynZEN: A Hybrid TTA/VLIW Architecture with a Distributed Register File
Zitatschlüssel HaMoJu2012
Autor Stefan Hauser and Nico Moser and Ben Juurlink
Jahr 2012
ISBN 978-1-4673-2221-8
DOI 10.1109/NORCHP.2012.6403142
Journal NORCHIP
Jahrgang 2012
Zusammenfassung The quest for higher performance within a certain power in the fields of demands unconventional architectural approaches. To this end, in this paper we present synZEN (sZ): a (micro-)architecture that combines features of very long instruction word (VLIW) and transport triggered architectures (TTAs) to cover the needs of different applications. SynZEN features a distributed register file (RF) (i.e., each functional unit (FU) has its own RF) and a wide memory connection to exploit spatial data locality. FPGA synthesis results demonstrate that due to the distributed RF the sZ design can be implemented in less area (in terms of FPGA slices) than existing TTA and VLIW designs. Furthermore, using two micro-benchmarks we show that because of the wide memory connection, sZ outperforms both the TTA as well as the VLIW design.
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