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Nexus++: a Hardware Task Management System for Multicore Systems


Since the trend of improving processor’s performance has shifted toward in- tegrating more cores on the same chip, several parallel programming models have been proposed that aim at relieving parallel programming. Examples include Google’s MapReduce, Intel’s TBB, and OmpSs.

is a promising approach, as it requires minimal effort of the pro- grammer to program in parallel since he or she can annotate the sequential application. The current software OmpSs runtime system, however, can be a bottleneck that limits the scalability of applications for large number of cores. Roughly speaking, the runtime system cannot compute task depen- dencies and attend to finished tasks fast enough to keep all cores busy. In this project we therefore develop Nexus++, a hardware system that provides architectural support for task-based parallel programming models such as OmpSs. The main goal of Nexus++ is to accelerate the task management responsibilities of the OmpSs runtime system.


Nexus++ in a multicore system
Lupe [1]

To develop a hardware task management system that

  • Accelerates task dependency resolution
  • Improves the performance of application with fine-grained tasks
  • Works for arbitrary task dependency graphs
  • Requires no or minimal support from the programmer.
  • Can be integrated in any type of multicore system.


  • Tamer Dallou [2]
  • Prof. Dr. Ben Juurlink [3]
  • Dr. Cor Meenderinck [4]
  • Nina Engelhardt [5]
  • Ahmed Elhossini [6]


This research is funded by the European Community’s Seventh Framework Programme [FP7/2007-2013] under the ENCORE Project [7], grant agreement n248647. It is also funded by the German-Jordanian university [8].

Student Projects

MSc project Design of a hardware task management unit for multicore systems, Mauricio Fayula Gonzalez.


Hardware-Based Task Dependency Resolution for the StarSs Programming Model
Zitatschlüssel Dallou:2012:Nexus
Autor Tamer Dallou and Ben Juurlink
Buchtitel 41st International Conference on Parallel Processing Workshops (ICPPW), SRMPDS'2012
Seiten 367 -374
Jahr 2012
ISBN ISBN 978-1-4673-2509-7
ISSN 1530-2016
DOI 10.1109/ICPPW.2012.53
Monat sept.
Link zur Publikation [9] Link zur Originalpublikation [10] Download Bibtex Eintrag [11]
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