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Low-power Parallel Computing on GPUs

Beschreibung

Lupe

Massively parallel GPUs are now being used in a great variety of market segments, ranging from video-games, to user interfaces, and to HPC. There are several signs, however, that computer and consumer technology industries are faced with major challenges in delivering improved performance and innovation for future entertainment devices. First, game developers have argued that while GPUs are increasing in performance, this is not leading to visual quality improvements because GPUs fundamentally restrict their flexibility. Second, there are signs that GPUs are approaching a "power wall", and architecture innovation is required now to circumvent this wall. Third, there is a lack of GPU tools available to compare multi-core processors (CPUs) to GPUs and to perform GPU program transformations to optimize for performance and power. To address these challenges, this project brings together commercial tools, applications and GPU designers, with academic researchers to analyze real-world mass-market software on comparable graphics processor architectures. The project results will help the design of next-generation GPUs, games consoles, and mobile phones, and help software developers produce graphically innovative software in the future. The main market areas for increased processor performance over the next few years are graphics and video-games. Therefore, the companies in the consortium are world leaders in real-time lighting for computer graphics (Geomerics), video game AI (AIGameDev.com), power-efficient GPU design (Think Silicon) and GPU tools (Codeplay), and the universities in the consortium are leading experts on low-power computer architecture (Uppsala) and parallel applications and multi-core architectures (TUB). The project seeks to achieve: power and bandwidth reductions of 2x or more on real-world software on next-generation GPUs, as well as GPU architecture designs that are capable of advanced real-time graphics techniques (such as radiosity and game AI) at power levels suitable for battery-powered devices.

At TU-Berlin we are mainly working on parallel application development for GPUs, power modeling and simulation of GPU architectures, architecture enhancements for improved scalability and programmability, and tools for automatic tunning of GPU applications.

More information available on the project web page: http://lpgpu.org/wp/

Beteilligte Personen

Beteilligte Personen
AES group principle investigator:

Prof. Dr. Ben Juurlink
LPGPU Technical lead: 

Mauricio Álvarez Mesa
PostDoc:
Ahmed Elhossini
PhD students: 

Jan Lucas,
Sohan Lal,
Biao Wang,
Tamer Dallou

Master student:

Michael Andersch
Diploma thesis:
Matthias Stroux
Gaststudenten:
Hakki Doganer Sümerkan,
Derya Gok

Publications

Analyzing GPGPU Pipeline Latency
Zitatschlüssel Andersch2014:gpu_latency
Autor Michael Andersch and Jan Lucas and Mauricio Alvarez-Mesa and Ben Juurlink
Buchtitel Proc. 10th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 14)
Jahr 2014
Monat July
Link zur Publikation Download Bibtex Eintrag

Förderung

Lupe

   

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