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TU Berlin

Inhalt des Dokuments

Sohan Lal

Contact

Contact information
Room:
E-N 646
Tel.:
+49 (0)30 314-22286
E-Mail

Office hours:
with appointment
Address:
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin

Publications

Jan Lucas and Sohan Lal and Michael Andersch and Mauricio Alvarez Mesa and Ben Juurlink (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator. Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS)


Jan Lucas and Sohan Lal and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2013). DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)


Sohan Lal and Jan Lucas and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2013). Exploring GPGPUs Workload Characteristics and Power Consumption. Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)


Sohan Lal and Jan Lucas and Michael Andersch and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2014). GPGPU Workload Characteristics and Performance Analysis. Proc. 14th Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 115-124.


Maurice Peemen and Runbin Shi and Sohan Lal and Ben Juurlink and Bart Mesman and Henk Corporaal (2016). The Neuro Vector Engine: Flexibility to Improve Convolutional Net Efficiency for Wearable Vision. Proc. Int. Conf on Design Automation, and Test in Europe,(DATE)


Sohan Lal and Jan Lucas and Ben Juurlink (2017). E²MC: Entropy Encoding based Memory Compression for GPUs. Proc. 31st IEEE Int. Parallel and Distributed Processing Symposium (IPDPS)


Biography

Lupe

Sohan Lal is working towards his PhD under the supervision of Prof. Ben Juurlink.
He completed his master of science by research in Information Technology from Indian Institute of Technology, Delhi (IITD) in 2011. Before that he worked at Shri Mata Vaishno Devi University in different capacities as Lecturer, Associate Lecturer, and Senior Technical Assistant. He received his bachelor in Computer Science and Engineering from Government college of engineering and technology (GCET), Jammu, India in 2003.

His research is focused on performance, power, and bottlenecks analysis of GPGPU workloads. Currently, he is working on memory divergence problems in GPUs. Broadly, he is interested in computer architecture, GPGPU, GPU power modeling and evaluation, and high performance computing.

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