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Research assistant (PhD Student or Postdoc) - 100% E13 TV-L Berliner Hochschulen.
Institut für Technische Informatik und Mikroelektronik / FG
Architektur eingebetteter Systeme
Reference number: IV-63/18 (starting at the earliest possible / limited until 30/11/2020 / closing date for applications 02/03/18). Part-time employment may be possible.
We are looking for either one post-doctoral researcher or PhD student to work with us on the CELERITY  project. The main goal is the design of a novel programming environment to develop energy- and performance- efficient, predictably scalable, and easy-to-program parallel applications targeting large-scale homogeneous and heterogeneous HPC clusters. The CELERITY environment includes compilation techniques based on the LLVM compiler, a distributed runtime system to handle MPI and OpenCL management, and a set of advanced modeling approaches based on machine learning and statistical modeling.
If you have experience with compilers, high-performance computing, parallel programming or you are strong in math, we are looking for you!
Working Location: TU Berlin, Berlin, Germany
- The successful candidate will join a vibrant international research team investigating parallel programming model and compiler techniques to optimize them, and will work on the DFG-funded research project CELERITY
- The project includes the opportunity to work on the fastest supercomputer of Europe and to collaborate with other international research groups
For more information on this position, please contact Dr. Biagio Cosenza (email@example.com, subject: JOB).
- a university degree (Master, Diplom or equivalent) in Computer Science, Computer Engineering, Applied Mathematics or similar
- experience with at least one parallel programming model such as OpenCL, CUDA, OpenMP, MPI and SYCL
- excellent programming skills in C/C++ and algorithmic coding
- fluent in English
- ability to work alone as well as in a team in a structured way
Ideally, candidates should have:
- practical experience with the LLVM compiler infrastructure
- basic knowledge of statistical modeling and machine learning
- confidence with parallel programming on HPC infrastructures
- experience in the usage of profiling tools and application benchmarking.
Please send your application with the reference number and the usual documents preferably by E-Mail to firstname.lastname@example.org or written to Technische Universität Berlin - Der Präsident - Fakultät IV, Institut für Technische Informatik und Mikroelektronik, FG Architektur eingebetteter Systeme, Dr. Cosenza, Sekr. EN 12, Einsteinufer 17, 10587 Berlin.
- link to the project on Gepris: http://gepris.dfg.de/gepris/projekt/360291326 
- link to the project on AES: http://www.aes.tu-berlin.de/menue/forschung/projekte/celerity/
Prof. Dr. Ben Juurlink
Room E-N 642
Room E-N 645
Mo, Tue, Wed and Thu 10:00 am - 12:00 am
or with appointment
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17- 6. OG
AES Flyer 2017
F&A Mündliche Prüfung Rechnerorganisation