TU Berlin

HOME AESHOME AES

AES Logo

Page Content

to Navigation

Welcome at AES

Lupe

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

News

12.06.17: AES-paper accepted at DSD 2017.

The paper "A Methodology for Predicting Application-specific Achievable Memory Bandwidth for HW/SW-Codesign" by Matthias Göbel, Ahmed Elhossini and Ben Juurlink has been accepted at DSD 2017 as a four-page paper. In this paper, we present a methodology that assists the designer in making good design decisions for FPGA-SoC-based systems using shared DDR memory for communication. Our methodology analyzes a software implementation of the application, generates a trace of the memory accesses of one function to be implemented in hardware and subsequently predicts the memory accesses of a functionally equivalent hardware implementation of the selected function. We furthermore propose an IP core that can perform these predicted memory accesses to estimate the achievable memory bandwidth between a functionally equivalent hardware implementation and shared memory. The resulting achievable memory bandwidth estimations demonstrate the feasibility of the presented methodology.

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications. The 20th edition will be held in Vienna, Austria between Aug 30th and Sep 1st.


12.06.2017: AES at SCOPES.

Prof. Ben Juurlink and Dr. Biagio Cosenza from AES are attending the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES) which is being held on June 12th and 13th, 2017 in Sankt Goar (Germany). Juurlink will present "The LPGPU2 Project - Low-Power Parallel Computing on GPUs", which is authored by Ben Juurlink, Martyn Bliss, Georgios Keramides and Jan Lucas. Cosenza will present "Stencil Autotuning with Ordinal Regression", which is authored by Biagio Cosenza, Juan Durillo, Stefano Ermon and Ben Juurlink.

The SCOPES workshop focuses on the software generation process for modern embedded systems. Topics of interest include all aspects of the compilation and mapping process of embedded single and multi-processor
systems.

For more information: http://www.scopesconf.org/

June 1, 2017, 14:00 - 15:00, "Dataflow programming for manycores". Prof. Dr.-Ing. Jeronimo Castrillon.

Lupe

Title: Dataflow programming for manycores

Presenter: Prof. Dr.-Ing. Jeronimo Castrillon - TU Dresden

Date and time: Thursday June 1, 2017, 14:00 - 15:00

Room: MA 005

Dataflow-based programming has proven to be a good programming model for heterogeneous multi-processor systems on chip in the signal processing and multimedia domains. This is due to a clear separation of computation and communication, well-defined semantics and a strict distributed state. This talk provides an overview of the MAPS framework for mapping dataflow applications to manycores. It then delves into the details of recently proposed techniques for improving tool scalability, and adaptability and robustness of the computed mappings. This includes (i) a mathematical way to exploit symmetries in the problem formulation to reduce the design space, (ii) a runtime approach to select and execute variants of an application under resource constraints, and (iii) an algorithmic approach based on design centering to improve mapping robustness. 

Jeronimo Castrillon is a professor in the Department of Computer Science at the TU Dresden, where he is also affiliated with the Center for Advancing Electronics Dresden (CfAED). He received the Electronics Engineering degree from the Pontificia Bolivariana University in Colombia in 2004, the master degree from the ALaRI Institute in Switzerland in 2006 and the Ph.D. degree (Dr.-Ing.) with honors from the RWTH Aachen University in Germany in 2013. His research interests lie on methodologies, languages, tools and algorithms for programming complex computing systems. He has more than 50 international publications and has been a member of technical program and organization committees in international conferences and workshops (e.g.,  DATE, Computing Frontiers, CGO, FPL, ICCS and ESWeek). He is also a regular reviewer for ACM and IEEE journals (e.g., IEEE TCAD, IEEE TPDS, ACM TODAES and ACM TECS). In 2014 Prof. Castrillon co-founded Silexica GmbH, a company that provides programming tools for embedded multicore architectures.


More news can be found here.

Research Seminar

  • 22.06.2017: "Overview of Ongoing Research Activities". Biagio Cosenza.
  • 29.06.2017-10:00: "SLC: Selective Lossy Compression to Leverage Memory Access Granularity". Sohan Lal.
more to: Research Seminar

Navigation

Quick Access

Schnellnavigation zur Seite über Nummerneingabe