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Welcome at AES


The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.


18.04.18: Sohan Lal Selected With Student Grant to Attend ACACES 2018.


Sohan Lal has been selected with student grant to attend the "Fourteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems" (ACACES 2018). The summer school is organized by the HiPEAC Network of Excellence. It is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture and compilation for computing systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry.
ACACES 2018 will take place in Fiuggi, Italy, from July 8th to July 14th, 2018.
For more information please visit: http://acaces.hipeac.net/2018/index.php

March 19-23, 2018: AES Presentation at DATE 2018.


Jan Lucas will present the paper "Optimal DC/AC Data Bus Inversion Coding" at DATE 2018 in Dresden. The paper is part of the "Emerging architectures and technologies for ultra low power and efficient embedded systems" Session on Thursday and presents a novel encoding technique that reduces the power consumption of the memory interface by up to 6%. DATE (Design, Automation and Test in Europe) is the European event for Electronic System Design and Test. More information can be found at https://www.date-conference.com/.

07.03.2018: AES-paper accepted at RAW 2018.


The paper “An Application-Specific Memory Management Unit for FPGA-SoCs” by Matthias Göbel, Ilja Behnke and Ben Juurlink has been accepted at the 25th Reconfigurable Architectures Workshop (RAW) at IPDPS 2018. In the paper, we present an MMU that can be used to enable memory virtualization in the FPGA part of an FPGA-SoC. Enabling memory virtualization reduces the overhead of implementing HW/SW-Codesign approaches significantly.

The 25th Reconfigurable Architectures Workshop (RAW 2018) will be held in Vancouver, British Columbia, Canada in May 2018. RAW 2018 is associated with the 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing.

More news can be found here.

Zusatzinformationen / Extras

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Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Request appointment

Secretary's office:
Sara Tennstedt
Room E-N 645
Tel. +49.30.314-73130
Consultation hours:
Mo, Tue, Wed and Thu 10:00 am - 12:00 am
or with appointment

Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17- 6. OG
D-10587 Berlin

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