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Welcome at AES

Lupe [1]

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.


20.10.17: AES Best-in-Class-Awards Summer 2017.

Lupe [2]

The Embedded Systems Architecture Group has given Best-in-Class Awards to the best students of the 2017 summer term. Kai Norman Clasen (Hot Topics in Embedded Systems), Leonard Wayne Hackel (Embedded Systems Architecture) and Rafael Fritsch (Advanced Computer Architectures) have shown outstanding performances in the respective courses. Congratulations!!!

18.10.2017: Ben Juurlink lead guest editor of special issue of International Journal of Reconfigurable Computing.

Lupe [3]

Prof. Ben Juurlink is lead guest editor of the special issue on “Approximating (Deep) Neural Networks and Approximate Computing Using Reconfigurable Hardware” of the International Journal of Reconfigurable Computing. The International Journal of Reconfigurable Computing [4] is published by Hindawi [5], which is one of the is one of the world’s largest publishers of peer-reviewed, fully Open Access journals. Among others, the EU is strongly in support of Open Access publications. Guest editors of this special issue are Georgios Keramides of Think Silicon, Patras, Greece; Stephan Wong of TU Delft in the Netherlands; Antonio Beck of Federal University of Rio Grande do Sul in Porto Alegre in Brazil; and Chao Wang of the University of Science and Technology China in Suzhou, China. The Call for Papers can be found here [6].

11.10.2017: Ben Juurlink at LPCP workshop.

Ben Juurlink is currently in College Station, Texas attending the 30th International Workshop on Languages and Compilers for Parallel Computing (LPCP) [7]. He will present the paper “Auto-Vectorization in C/C++ Compilers: the Impact of Loop-Level Vectorization and Superword Level Parallelism” co-authored by Angela Pohl, Biagio Cosenza and Ben Juurlink, which has been accepted as a poster presentation, as well as give an invited talk about "Autotuning Stencil Computations with Structural Ordinal Regression Learning”.

More news can be found here [8].

Current Projects [9]

  • LPGPU2 [10]
  • High Performance Video Coding [11]
  • CompVision: Computer Vision Library for Reconfigurable Architectures [12]
more to: Current Projects [13]

Courses in WS 17/18 [14]

  • Rechnerorganisation Praktikum [15]
  • Rechnerorganisation (VL + Üb) [16]
  • Multicore Systems (VL + Üb) [17]
  • Recent Advances in Computer Architecture [18]
  • AES Bachelor Project [19]
  • Computer Arithmetic: Circuit Perspective [20]
  • Hardware-Praktikum [21]
  • Compiler Design (VL + Üb) [22]

  • F&A Mündliche Prüfung Rechnerorganisation [23]
more to: Courses in WS 17/18 [24]

Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Request appointment

Secretary's office:
Sara Tennstedt
Room E-N 645
Tel. +49.30.314-73130
Consultation hours:
Mo, Tue, Wed and Thu 10:00 am - 12:00 am
or with appointment
Contact [25]

Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17- 6. OG
D-10587 Berlin

AES Flyer:
AES Flyer 2017

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