Inhalt des Dokuments
Welcome at AES
- © AES
The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.
03.08.2017: PEGPUM 2018 workshop proposal accepted.
- © LPGPU2
The 6th LPGPU2 Workshop on Power-Efficient GPU and Many-core Computing has been accepted by the HiPEAC 2018 organization committee as a full day workshop. The workshop will consists of a mix of (a) presentations of short papers submitted in response to the call for papers and reviewed by the organizers, (b) presentations of LPGPU2 consortium members of project results, (c) demonstrations and short tutorials by LPGPU2 consortium members on how to use the tools developed in the LPGPU2 project, and (d) one invited talk by a key person from the mobile or high-performance GPU industry. more
20.07.2017, 10:30, EN 643/644: "Perceptron Learning for Reuse Prediction". Elvira Teran.
The disparity between last-level cache and memory latencies motivates the search for efficient cache management policies. Recent work in predicting reuse of cache blocks enables optimizations that significantly improve cache performance and efficiency. However, the accuracy of the prediction mechanisms limits the scope of optimization. This paper proposes perceptron learning for reuse prediction. more
19.07.2017: Dr. Cosenza to moderate a panel on "Programming Models for the ExaScale Era" at HPCS 2017.
- © Biagio Cosenza
Dr. Biagio Cosenza will be
at the IEEE International Conference on High Performance Computing
& Simulation (HPCS 2017) in Genoa, Italy.
On Wednesday, 19 July, he will moderate the panel on "Programming Models for the Exascale Era". The panel will be held in the Aurea Ballroom of the Grand Hotel Savoia at 16:30. more
Please note that the secretary’s office will reopen on 11
We apologize for any inconvenience.
Prof. Dr. Ben Juurlink
Room E-N 642
Sara Tennstedt (parental leave)
Room E-N 645
Mo 9:00 am - 12:00 am
Tue 3:00 pm -6:00 pm
or with appointment
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17- 6. OG
AES Flyer 2017