Inhalt des Dokuments
Welcome at AES
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The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.
January 22-24, 2018: AES presentations at HiPEAC18.
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Jan Lucas, Matthias Göbel and Nadjib Mammeri visited the 13th HiPEAC Conference in Manchester from Jan 22nd to Jan 24th. They presented their work both by giving invited talks at the PEGPUM workshop, which was co-organized by AES, as well as by taking part in the poster sessions. The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems.
More information can be found at https://www.hipeac.net/2018/manchester/ .
13.12.2017: Tamer Dallou successfully completed his PhD defense.
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M.Sc. Tamer Dallou successfully completed his PhD defense on Wednesday 13th December 2017. His thesis title was: "Enhancing the Scalability of Many-core Systems – Towards Utilizing Fine-Grain Parallelism in Task-Based Programming Models”.
Congratulation Dr. Dallou for your success and we wish you the best in your future!
11.12.2017: Paper from AES/CERN collaboration accepted at PDP 2018.
The paper “Accelerating the RICH Particle Detector Algorithm on Intel Xeon Phi” written by Christina Quast, Angela Pohl, Biagio Cosenza, Ben Juurlink, as well as Rainer Schwemmer (CERN) was accepted at the 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2018).
In the paper, the authors show how an algorithm for particle classification was sped up on an Intel Xeon Phi platform using multiple optimization techniques. The work will presented as a full paper in the “GPU and Many Integrated Core” special session.
More information can be found at http://www.pdp2018.org/ .
Prof. Dr. Ben Juurlink
Room E-N 642
Room E-N 645
Mo, Tue, Wed and Thu 10:00 am - 12:00 am
or with appointment
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17- 6. OG
AES Flyer 2017