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Welcome at AES

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The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. We focus on the design, implementation and optimization of high performance embedded systems; taking into account the interactions between applications, tools, and architectures. In addition to high performance we also aim at improving energy efficiency, programmability, predictability, error resilience, as well as other features of emerging computer systems.

April 29th, 2015: Prof. Juurlink in PhD defence committee in Eindhoven.

https://www.tue.nl/

On April 29 Ben Juurlink is a member of the PhD defence committee of Raymond Frijns, who defences his dissertation entitled “Platform-based Design for High-Performance Mechatronic Systems” at the Technical University of Eindhoven. more to: April 29th, 2015: Prof. Juurlink in PhD defence committee in Eindhoven.

May 3-5, 2015: Paper "High Performance Memory Accesses on FPGA-SoCs: A quantitative analysis" accepted at FCCM 2015.

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The paper „High Performance Memory Accesses on FPGA-SoCs: A quantitative analysis“ by Matthias Göbel, Chi Ching Chi, Mauricio Alvarez-Mesa and Ben Juurlink was accepted as a poster at FCCM 2015. The conference takes place between May 3-5 in Vancouver, BC. more to: May 3-5, 2015: Paper "High Performance Memory Accesses on FPGA-SoCs: A quantitative analysis" accepted at FCCM 2015.

May 7+8, 2015: Three papers from the AES group are accepted for publication in the 26th PARS-Workshop.

Three papers from the AES group are accepted for publication in the 26th PARS-Workshop that will be organized by the Universität Potsdam on May 7 and 8, 2015, in the city of Potsdam, Germany. The papers are going to be presented during the workshop. The accepted papers are: 1- "High performance CCSDS image data compression using GPGPUs for space applications" by Sunil Chokkanathapuram Ramanarayanan, Kristian Manthey and Ben Juurlink. 2- "A Proximity Scheme for Instruction Caches in Tiled CMP Architectures" by Tareq Alawneh, Chi Chi, Ahmed Elhossini and Ben Juurlink. 3- "Real-Time Vision System for License Plate Detection and Recognition on FPGA" by Farid Rosli, Ahmed Elhossini and Ben Juurlink. more to: May 7+8, 2015: Three papers from the AES group are accepted for publication in the 26th PARS-Workshop.

Research Seminar

  • April 23th, 2015-10:00am: "Effcient Real-Time FPGA Implementation of Kaze Features". Lester Kalms.
more to: Research Seminar

Zusatzinformationen / Extras

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Auxiliary Functions

Chair:
Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Fax +49.30.314-22943
Consultation hour:
Tue 4:00-5:00 p.m. only after making an appointment via the secretary!

Secretary's office:
Angela Nicko
Jana Pilz
Room E-N 645
Tel. +49.30.314-73130
Fax +49.30.314-22943
Opening Hours:
Mo-Wed 9:00 am -12:00 (Angela Nicko)
Thur 9:00 am - 12:00 (Jana Pilz)
and with registration


Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin
Germany