direkt zum Inhalt springen

direkt zum Hauptnavigationsmenü

Sie sind hier

TU Berlin

Inhalt des Dokuments

Welcome at AES

Bild
Lupe

The Embedded Systems Architecture (Architektur eingebetteter Systeme, AES) group investigates and teaches the field of computer architecture, ranging from low-power embedded systems to massively parallel high-performance systems. The field of computer architecture has undergone drastic changes in recent years. While for several decades the main objective has been to increase clock frequency and to exploit higher levels of instruction-level parallelism, the current trend is toward symmetric or heterogeneous multi- and many-core architectures. In order to fully leverage such architectures, applications have to be adapted to and optimized for such systems, and architecture support is needed to increase their programmability.

Similarly, the importance of embedded systems, which must fulfill functional as well as non-functional requirements, has increased strongly. In this area we focus on the hardware-software codesign of such systems under specific constraints. Multi-core systems are also increasingly being deployed in embedded systems.

Current News

Paper "An Efficient and Flexible FPGA Implementation of a Face Detection System" accepted in FPGA-2015 (Poster session)

17. November 2014

Bild

The paper "An Efficient and Flexible FPGA Implementation of a Face Detection System" by Hichem Ben Fakeh, Ahmed Elhossini, and Ben Juurlink was accepted as a poster in FPGA 2015, Monterery, California. The abstract will appear in the conference procedure in February 2015. more to: Paper "An Efficient and Flexible FPGA Implementation of a Face Detection System" accepted in FPGA-2015 (Poster session)

Research

Research Seminar

  • November 27th, 2014-10:00 to 10:30am-Rate Control Optimization in the AES HEVC Encoder- Sergio Sanz-Rodriguez.
  • November 27th, 2014-10:30 to 11:00am-Ultra-Low Power Parallel Architectures- Daniele Bortolotti.
more to: Research Seminar

Research

Current Projects

  • Low-power Parallel Computing on GPUs
  • High Performance Video Coding
  • CompVision: Computer Vision Library for Reconfigurable Architectures
  • Nexus++: a Hardware Task Management System for Multicore Systems
more to: Current Projects

Study & Teaching

Lehrveranstaltungen in WS 14/15

  • Rechnerorganisation (Vorlesung und Übungen)
  • Rechnerorganisation Praktikum
  • Architektur eingebetteter Systeme
  • Multicore Architectures
  • Recent Advances in Computer Architecture
  • AES Bachelor Projekt (ABP)
  • Computer Arithmetic: Circuit Perspective
  • Hardware-Praktikum.
more to: Lehrveranstaltungen in WS 14/15

Zusatzinformationen / Extras

Quick Access:

Schnellnavigation zur Seite über Nummerneingabe

Auxiliary Functions

Chair:
Prof. Dr. Ben Juurlink
Room E-N 642
Tel. +49.30.314-73130/73131
Fax +49.30.314-22943
Consultation hours:
Tue 4:15-5:15 p.m.
or after making an appointment via the secretary

Secretary's office:
Angela Nicko
Jana Pilz
Room E-N 645
Tel. +49.30.314-73130
Fax +49.30.314-22943
Opening Hours:
Mo-Wed 9:00 am -12:00 (Angela Nicko)
Thur 9:00 am - 12:00 (Jana Pilz)
and with registration


Postal address:
Technische Universität Berlin
Institut für Technische Informatik und Mikroelektronik (TIME)
Sekretariat EN 12
Einsteinufer 17
D-10587 Berlin
Germany


Due to a further education course, the secretary’s office will be closed on Monday 1 December from 9:00 to 11:30 am. We apologize for any inconvenience.