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Low-power Parallel Computing on GPUs



Massively parallel GPUs are now being used in a great variety of market segments, ranging from video-games, to user interfaces, and to HPC. There are several signs, however, that computer and consumer technology industries are faced with major challenges in delivering improved performance and innovation for future entertainment devices. First, game developers have argued that while GPUs are increasing in performance, this is not leading to visual quality improvements because GPUs fundamentally restrict their flexibility. Second, there are signs that GPUs are approaching a "power wall", and architecture innovation is required now to circumvent this wall. Third, there is a lack of GPU tools available to compare multi-core processors (CPUs) to GPUs and to perform GPU program transformations to optimize for performance and power. To address these challenges, this project brings together commercial tools, applications and GPU designers, with academic researchers to analyze real-world mass-market software on comparable graphics processor architectures. The project results will help the design of next-generation GPUs, games consoles, and mobile phones, and help software developers produce graphically innovative software in the future. The main market areas for increased processor performance over the next few years are graphics and video-games. Therefore, the companies in the consortium are world leaders in real-time lighting for computer graphics (Geomerics), video game AI (AIGameDev.com), power-efficient GPU design (Think Silicon) and GPU tools (Codeplay), and the universities in the consortium are leading experts on low-power computer architecture (Uppsala) and parallel applications and multi-core architectures (TUB). The project seeks to achieve: power and bandwidth reductions of 2x or more on real-world software on next-generation GPUs, as well as GPU architecture designs that are capable of advanced real-time graphics techniques (such as radiosity and game AI) at power levels suitable for battery-powered devices.

At TU-Berlin we are mainly working on parallel application development for GPUs, power modeling and simulation of GPU architectures, architecture enhancements for improved scalability and programmability, and tools for automatic tunning of GPU applications.

More information available on the project web page: http://lpgpu.org/wp/

People on the project

People on the project
AES group principle investigator:

Prof. Dr. Ben Juurlink
LPGPU Technical lead: 

Mauricio Álvarez Mesa
Ahmed Elhossini
PhD students: 

Jan Lucas,
Sohan Lal,
Biao Wang,
Tamer Dallou
Master student:

Michael Andersch

Diploma thesis:
Matthias Stroux
Visitor students:
Hakki Doganer Sümerkan,
Derya Gok


Jan Lucas and Sohan Lal and Michael Andersch and Mauricio Alvarez Mesa and Ben Juurlink (2013). How a Single Chip Causes Massive Power Bills - GPUSimPow: A GPGPU Power Simulator. Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software

Jan Lucas and Sohan Lal and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2013). DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads. Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)

Sohan Lal and Jan Lucas and Mauricio Alvarez-Mesa and Ahmed Elhossini and Ben Juurlink (2013). Exploring GPGPUs Workload Characteristics and Power Consumption. Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)

Tamer Dallou and Ahmed Elhossini and Ben Juurlink (2013). FPGA-Based Prototype of Nexus++ Task Manager. 6th Workshop on Many-Task Computing on Clouds, Grids, and Supercomputers (MTAGS) 2013, Co-located with SC 2013




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