Inhalt des Dokuments
High Performance Video Coding
Computer architecture and video coding have mutually influenced each other during their technological advancement. Video codecs have improved their compression capabilities over time by introducing advanced coding tools that usually require more computational resources with each new generation. At the same time, user demands for better quality have pushed the adoption of high quality video systems with HD and UHD resolutions and increased bitdepths and color formats, which require even more computation resources. Computer architectures, on the other hand, have improved their performance over time with a combination of technology and an increased support of parallelism, mainly Data Level Parallelism (DLP) and Thread Level Parallelism (TLP).
Our main research goal is to optimize video codecs such as H.264/AVC and HEVC/H.265 in order to obtain efficient implementations on contemporary computer architectures. We work on general algorithmic optimizations as well as optimizations for better use of hardware resources.
- Implementations on general purpose processors. We work on adaptations and optimizations of video codecs in order to obtain the maximum performance that the architecture can provide. This includes parallelization for multi- and many-core architectures, GPU acceleration, SIMD vectorization, and memory layout optimizations. The main objective is to find an appropriate mapping of the type of parallelism present in video codecs to the type of parallelism offered by recent parallel computer architectures. We also investigate how to reduce power consumption and increase energy efficiency of software video (de)coders by using the low power modes included in most recent microprocessors.
- Implementations using hardware/software codesign. Although general purpose processors can provide the required performance for video codecs their power, energy and cost is not acceptable in all applications. As an alternative, specially in mass-market multimedia devices, SoCs with dedicated hardware components are used. To reduce the cost of production of these devices as well as their energy consumption it is crucial to find the right partitioning between hardware and software implementations and to apply efficient interconnect technologies. Our group therefore investigates methods for high-speed, low-cost encoding as well as decoding of video streams by using modern HW/SW codesign techniques and state-of-the-art FPGAs and embedded processors.
- Algorithms for efficient video coding. State-of-the art video codecs include many coding tools each one allowing multiple operation modes. Full search approaches can give the maximum compression and quality levels but at the cost of an unpractical complexity. We investigate on algorithms for performing efficient video coding using the computational resources offered by state-of-the-art microprocessors. The main research objective is to find the best quality and compression tradeoff when using all the computational resources of recent high performance microprocessors (with ILP, SIMD and multicore optimizations enabled)
- Highly scalable parallel H.264/AVC decoder.
We have developed a parallel H.264/AVC decoder that can scale to many-core architectures. There are two implementations: one using pthreads, and the other one using the OmpSs programming model. The code is part of the Starbench benchmark developed by our group.
* Starbench (GZ, 630,1 KB)
* If you have any questions regarding Starbench, please write a mail to: email@example.com.
- OpenCL H.264/AVC video decoder for GPUs.
Our OpenCL h.264/AVC decoder offloads inverse transform and motion compensation onto OpenCL devices. To use it you need an OpenCL supported device, driver, and corresponding OpenCL SDK installed.
* OpenCL decoder (GZ, 394,5 KB)
* If you have any questions regarding h.264 OpenCL decoder, please write a mail to: firstname.lastname@example.org