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The CluMP! project was funded by the faculty IV to keep digital design knowledge in house and make it accessible to other faculty members without any experience in this area.
The technical core foundation will be a tightly coupled FPGA based cluster with focus on low cost, low energy, flexibility and capabilities for academic research.
The two main components are the FPGA and the µProzessor. Both have the early stage of their product life in common and are therefore equipped with state of the art features and interfaces as well as low power technologies.
Xilinx Kintex XC7325T
- part of a new midway high end family fabricated in a 28nm low power process
- FFG 900 package with 16 serdes lines @12.5Gbps (GTX)
- DDR 3 SDRAM and QDR II+ SRAM
PowerPC APM 86290
- Dualcore @1.4GHz
- SATA 2, Gb ethernet, DDR 3 SDRAM, x4 PCI express 2
Both parts are connected via a powerful x4 PCI express 2 interface for tightly coupled data exchange with high bandwitdh. Beside configurations tasks the µProcessor is high performance enough to execute profiling threads, control tasks in hardware-/software codesign settings or data management.
Eight of the GTX high speed serial FPGA links are used to connect the nodes with data sources and sinks. Six of them are singled out to connect nodes (and therefore FPGAs) directly using a 3D Torus topology. The remaining two can be used for 10Gb Ethernet (in case of a hierarchical cluster with a top switch based topology) or FiberChannel storage systems or other purpose. To achieve this flexibility level for use of the high speed serial links we choose SFP+ infrastructure as physical connectors. In total 160 Gbps bandwidth is at one node disposal.
Several tasks have to be investigated and implemented:
- using node spanned logic resources vs. per node computing elements
- data flow monitoring and profiling supported by hardware counter
- unified address space models for local and global data flow
- frame based vs. streaming data access
- low latency interfaces.
- Nico Moser
- Prof. Dr. Ben Juurlink